Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer
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An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.
KeywordsEnhanced dual-gate Lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) Partial buried layer Specific on-resistance
Lateral double-diffused metal-oxide-semiconductor transistor
Ultra-shallow trench isolation
With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (Ron,sp) and maximizing off-state breakdown voltage (BV) [1, 2, 3, 4, 5, 6, 7, 8, 9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of Ron,sp vs. BV for LDMOS devices [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]. In our previous work, the LDMOS with ultra-shallow trench isolation (USTI) was proposed . The depth and corner angel of USTI were optimized to achieve best-in-class performance. However, for the low voltage LDMOS, the drift region is losing domination in Ron,sp and the contribution of the channel region cannot be ignored.
In this work, a novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is investigated. The physical models IMPACT.I, BGN, CONMOB, FLDMOB, SRH, and SRFMOB are used in numerical simulation. On-resistance analytical model is proposed to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. Based on the model, N-buried layer and partial P-buried layer are optimized to achieve low Ron,sp and high BV.
Results and Discussion
The key size of the novel device
Figure 1b shows the schematic equivalent on-resistance model for the proposed LDMOS. The total on-resistance is considered as the resistance of the drift region (Rd) and the resistance of the channel region (Rc) in series. In the channel region, surface channel conduction path parallels the trench channel conduction path. Thus, Rc is equal to (Rchs + Racc)//(Rcht + Rnb), where Rchs, Racc, Rcht, and Rnb are the resistances of the surface-gate channel, the accumulation region, the trench gate channel, and the N-buried layer, respectively. Based on the proposed on-resistance model, the reduction of Rc would achieve by decreasing Rnb without affecting the other performances, because the other resistances are mainly determinate by the process technology, operation voltage, and threshold voltage. The Rd has been reduced by introducing P-buried layer under N-drift region to enhance the Reduce Surface-field (RESURF) effect in our previous work. In this work, the partial P-buried layer is adopted to improve the BV while maintaining the low Rd.
A novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is proposed and investigated by numerical simulation in this paper. N-buried layer with high doping concentration is utilized to achieve enhanced dual-gate with reducing Rc. Partial P-buried layer is introduced under the N-drift region to enhance BV with keeping charge balance. The fabrication process of the LDMOS in this work is compatible with the existing BCD technology reported in our previous work. The result shows that the Ron,sp of the proposed LDMOS is reduced by 37% at BV of 43 V compared with previous work. With the semiconductor processing technology going to nanometer level, the Ron,sp can reduce further with channel length decrease.
This work was supported in part by the National Natural Science Foundation of China under Contract 61674027, in part by the China Postdoctoral Science Foundation Funded Project under Grant 2017 M612942, and in part by the Natural Science Foundation of Guangdong Province under Grant 2016A030311022 and 2018A030310015, in part by the Applied Fundamental Research Project of Sichuan Province under Grant 18YYJC0482, and in part by the Fundamental Research Funds for the Central Universities under Grant ZYGX2016J210.
Availability of Data and Materials
All data generated or analyzed during this study are included in this published article.
ZW proposed the novel structure and was a major contributor in writing the manuscript. ZY built, deduced, and calculated the analytical model. XZ verified the analytical model by simulation software. Other authors offered comments and revised the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
- 1.Disney D, Chan W, Lam R, Blattner R, Ma S, Seng W, Chen J-W, Cornell M, Williams R (2008) 60 V lateral trench MOSFET in 0.35 μm technology. Proc ISPSD:24–27. https://doi.org/10.1109/ISPSD.2008.4538888
- 3.Shimamoto S, Yanagida Y, Shirakawa S, Miyakoshi K, Imai T, Oshima T, Sakano J, Wada S (2011) High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology. Proc ISPSD:44–47. https://doi.org/10.1109/ISPSD.2011.5890786
- 4.Fujii H, Tokumitsu S, Mori T, Yamashita T, Maruyama T, Maruyama T, Maruyama Y, Nishimoto S, Arie H, Kubi S, Ipposhi T (2017) A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications. Proc ISPSD:73–76. https://doi.org/10.23919/ISPSD.2017.7988896.
- 5.Huang T-Y, Liao W-Y, Yang C-Y, Huang C-H, Yeh W-CV, Huang C-F, Lo K-H, Chiu C-W, Kao T-C, Su H-D, Chang K-C (2014) 0.18 um BCD technology with best-in-class LDMOS from 6 V to 45 V. Proc ISPSD:179–181. https://doi.org/10.1109/ISPSD.2014.6856005
- 6.Lee K, Jeon H, Cho B, Cho J, Pang Y-S, Moon J, Kwon S, Hébert F, Lee J, Lee T (2013) 0.35 μm, 30V fully isolated and low-Ron nLDMOS for DC-DC applications. Proc ISPSD:163–166. https://doi.org/10.1109/ISPSD.2013.6694454
- 7.Jang J, Cho K-H, Jang D, Kim M, Yoon C, Park J, Oh H, Kim C, Ko H, Lee K, Yi S (2013) Interdigitated LDMOS. Proc ISPSD:245–248. https://doi.org/10.1109/ISPSD.2013.6694462.
- 8.Roggero R, Croce G, Gattari P, Castellana E, Molfese A, Marchesi G, Atzeni L, Buran C, Paleari A, Ballarin G, Manzini S, Alagi F, Pizzo G (2013) BCD8sP: an advanced 0.16 μm technology platform with state of the art power devices. Proc ISPSD:361–364. https://doi.org/10.1109/ISPSD.2013.669442.
- 9.Ko K-S, Lee S-H, Kim D-H, Eum J-N, Park S-K, Cho I-W, Kim J-H, Yoo K-D (2013) HB1340 - advanced 0.13 um BCDMOS technology of complimentary LDMOS including fully isolated transistors. Proc ISPSD:159–162. https://doi.org/10.1109/ISPSD.2013.6694453.
- 10.van der Pol JA, Ludikhuize AW, Huizing HGA, vanVelzen B, Hueting RJE, Mom JF, van Lijnschoten G, Hessels GJJ, Hooghoudt EF, van Huizen R, Swanenberg MJ, Egbers JHHA, van den Elshout F, Koning JJ, Schligtenhorst H, Soeteman J (2000) A-BCD: an economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications. Proc ISPSD:327–330. https://doi.org/10.1109/ISPSD.2000.856836
- 11.Wei J, Luo X, Ma D, Wu J, Li Z, Zhang B (2016) Accumulation mode triple gate SOI LDMOS with ultralow on-resistance and enhanced transconductance. Proc ISPSD:171–174. https://doi.org/10.1109/ISPSD.2016.7520805
- 17.Iqbal MM-H, Udrea F, Napoli E (2009) On the static performance of the RESURF LDMOSFETS for power ICs. Proc ISPSD:247–250. https://doi.org/10.1109/ISPSD.2009.5158048.
- 18.Yoo A, Ng JCW, Sin JKO, Ng WT (2010) High performance CMOS-compatible super-junction FINFETs for sub-100 V applications. IEDM Tech Dig:20.7.1–20.7.4. https://doi.org/10.1109/IEDM.2010.5703402
- 19.Nitta T, Yanagi S, Miyajima T, Furuya K, Otsu Y, Onoda H, Hatasako K (2006) Wide voltage power device implementation in 0.25 μm SOI BiC-DMOS. Proc ISPSD:1–4. https://doi.org/10.1109/ISPSD.2006.1666141
- 20.Yamaguchi H, Urakami Y, Sakakibara J (2006) Breakthrough of on-resistance Si limit by super 3D MOSFET under 100 V breakdown voltage. Proc ISPSD:1–4. https://doi.org/10.1109/ISPSD.2006.1666071
- 21.Jin F, Liu D, Xing J, Yang X, Yang J, Qian W, Yue W, Wang P, Qiao M, Zhang B (2017) Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18 μm BCD technology. Proc ISPSD:295–298. https://doi.org/10.23919/ISPSD.2017.7988962
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