High mobility Ge pMOSFETs with amorphous Si passivation: impact of surface orientation
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We report the amorphous Si passivation of Ge pMOSFETs fabricated on (001)-, (011)-, and (111)-orientated surfaces for advanced CMOS and thin film transistor applications. Amorphous Si passivation of Ge is carried out by magnetron sputtering at room temperature. With the fixed thickness of Si tSi, (001)-oriented Ge pMOSFETs achieve the higher on-state current ION and effective hole mobility μeff compared to the devices on other orientations. At an inversion charge density Qinv of 3.5 × 1012 cm−2, Ge(001) transistors with 0.9 nm tSi demonstrate a peak μeff of 278 cm2/V × s, which is 2.97 times higher than the Si universal mobility. With the decreasing of tSi, ION of Ge transistors increases due to the reduction of capacitive effective thickness, but subthreshold swing and leakage floor characteristics are degraded attributed to the increasing of midgap Dit.
KeywordsGermanium MOSFET Amorphous Si passivation Mobility Surface orientation
Atomic layer deposition
Boron fluoride ion
Capacitive effective thickness
High-resolution transmission electron microscope
Metal-oxide-semiconductor field-effect transistors
Tetrakis (dimethylamido) hafnium
Germanium (Ge) has been attracting tremendous research interests for advanced CMOS and thin film transistor applications due to its higher hole mobility and lower thermal budget processing compared to Si [1, 2, 3, 4, 5, 6]. To achieve the high channel mobility, the surface passivation process leading to a high interface quality is required before gate stack formation. Several surface passivation techniques have been developed to deliver the carrier mobility benefits in Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) [1, 2, 7, 8, 9, 10]. Among these techniques, a silicon (Si) cap passivated on Ge has been the hotspot in recent years, due to its advantages of effective suppressing of interface states and good thermal stability and reliability . Formation of Si passivation cap has been widely studied using chemical vapor deposition (CVD) with precursors of SiH4 , Si2H6 , Si3H8 , and E-beam evaporation . Although CVD method could provide the more uniform passivation layer over physical vapor deposition (PVD), its passivation rate has the strong correlation in channel surface orientation and the process temperature. PVD technique could provide the improved passivation rate even at room temperature, which has the advantages of low thermal budget and low cost, making it more suitable for the thin film transistors and back-end-of-line 3D integration applications. In this letter, we fabricated high mobility Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces utilizing amorphous Si passivation by magnetron sputtering. Significantly improved effective hole mobility μeff is achieved in Ge transistors compared to the Si universal mobility. Impacts of surface orientation and thickness of amorphous Si tSi on the boosting effect of amorphous Si passivation on μeff are studied.
Results and discussion
Key electrical performance of Ge pMOSFETs on the different orientations
Midgap Dit (cm− 2 eV − 1)
ION@VDS = − 0.5 V, VGS-VTH = − 0.8 V
(LG = 3 μm)
Qinv = 5 × 1012 cm− 2
(cm2/V × s)
9.3 × 1012
1.4 × 1013
2.1 × 1013
1.8 × 1013
2.7 × 1013
Ge pMOSFET passivated by amorphous Si are demonstrated on (001)-, (011)-, and (111)-oriented substrate. With a tSi of 0.9 nm, the improved ION and SS characteristics are obtained in (001)-oriented Ge pMOSFETs in comparison with the devices on (011) and (111) orientations, due to the higher μeff and lower midgap Dit. Ge(001) pMOSFETs with 0.9 nm tSi achieve a peak mobility of 278 cm2/V s at a Qinv of 3.5 × 1012 cm−2, which is 2.97 times higher than the Si universal mobility. It is demonstrated that ION of the devices is improved with the decreasing of tSi due to the reduction of CET. But Ge pMOSFETs with thicker tSi exhibit the superior subthreshold swing and leakage floor, owing to that midgap Dit can be reduced by increasing tSi.
The authors acknowledge support from the National Natural Science Foundation of China under Grant No. 61534004, 61604112, and 61622405.
Availability of data and materials
The datasets supporting the conclusions of this article are included within the article.
HL carried out the experiments and drafted the manuscript. GQH and YL supported the study and helped to revise the manuscript. XST and JCY helped to carry out the measurements. YH provided constructive advice in the drafting. All the authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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- 2.Mitard J, Jaeger BD, Leys FE, Hellings G, Martens K, Eneman G, Brunco DP, Loo R, Lin JC, Shamiryan D, Vandeweyer T, Winderickx G, Vrancken E, Yu CH, Meyer KD, Caymax M, Pantisano L, Meuris M, Heyns MM (2008) Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability. In: IEDM Tech Dig, pp 873–876 https://doi.org/10.1109/IEDM.2008.4796837 Google Scholar
- 3.Vincent B, Loo R, Vandervorst W, Delmotte J, Douhard B, Valev VK, Vanbel M, Verbiest T, Rip J, Brijs B, Conard T, Claypool C, Takeuchi S, Zaima S, Mitard J, Jaeger BD, Dekoster J, Caymax M (2011) Si passivation for Ge pMOSFETs: impact of Si cap growth conditions. Solid State Electron 60:116–121CrossRefGoogle Scholar
- 6.Sadoh T, Kamizuru H, Kenjo A, Miyao M (2006) Low-temperature formation (< 500 °C) of poly-Ge thin-film transistor with NiGe Schottky source/drain. Appl Phys Lett 89:192–114Google Scholar
- 12.Mitard J, Martens K, Jaeger BD, Franco J, Shea C, Plourde C, Leys FE, Loo R, Hellings G, Eneman G, Wang WE, Lin JC, Kaczer B, DeMeyer K, Hoffmann T, DeGendt S, Caymax M, Meuris M, Heyns MM (2009) Impact of epi-Si growth temperature on Ge-pFET performance. In: European Solid State Device Research Conference, pp 411–414 https://doi.org/10.1109/ESSDERC.2009.5331351 Google Scholar
- 16.Greve DW (1998) Field effect devices and application: devices for portable, low-power, and imaging systems, 1st edn. Prentice-Hall, EnglewoodGoogle Scholar
- 18.Pillarisetty R, Chu-Kung B, Corcoran S, Dewey G, Kavalieros J, Kennel H, Kotlyar R, Le V, Lionberger D, Metz M, Mukherjee N, Nah J, Rachmady W, Radosavljevic M, Shah U, Taft S, Then H, Zelick N, Chau R (2010) High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III-V CMOS architecture. In: IEDM Tech. Dig, pp 150–153 https://doi.org/10.1109/IEDM.2010.5703312 Google Scholar
- 19.Mitard J, Witters L, Vincent B, Franco J, Eavia P, Hikavyy A, Eneman G, Loo R, Brunco DP, Kabir N, Bender H, Sebaai F, Vos R, Mertens P, Milenin A, Vecchio E, Ragnarsson L-Å, Collaert N, Thean A (2013) First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects. In: VLSIT Dig, pp T20–T21Google Scholar
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