RTN and Annealing Related to Stress and Temperature in FIND RRAM Array
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In this work, an observation on random telegraph noise (RTN) signal in the read current of a FinFET dielectric RRAM (FIND RRAM) device is presented. The RTN signal of a FIND RRAM cell is found to change after the device being subjected to cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more frequent and intense RTN signals. The increase of noise levels in FIND RRAM cells can be alleviated generally by high temperature anneal, and with this concept, an on chip annealing scheme is proposed and demonstrated.
KeywordsRandom telegraph noise Advanced FinFET technology RRAM Anneal
- FIND RRAM
Fin field-effect transistor dielectric resistive random access memory
High resistance state
Low resistance state
Random telegraph noise
Transition metal oxide
Continuous scaling of CMOS technology improved the characteristics and performance of integrated circuits drastically in the past decade. However, as the technology node is scaled down below 20 nm, variations due to single atom/electron in device characteristics increases, for example, random dopant fluctuations (RDF), and thus bringing forth fundamental issues that cannot be overseen . For instance, any variations in the number of carriers or structural defects have a much larger impact on the output and performance in a scaled device, and the effects of device scaling on variability due to RDF and gate line-edge roughness (LER) have also been reported [2, 3, 4]. Random telegraph noise (RTN) is thought to be another major challenge for devices with small area, such as NAND Flash and RRAMs [5, 6, 7, 8, 9, 10, 11]. In this work, we investigate the RTN noise in an n-channel FinFET-based FIND RRAM cell, which has already been successfully implemented in standard logic process in 1kbit arrays . Changes in the RTN in response to cycling stresses and high-temperature bake are observed. In this work, the effects of stress and temperature on the RTN noise in FIND RRAM cells is studied, and an on-chip annealing scheme is proposed to alleviate the after cycling time-variant read current noise.
Background and Methods
It is well established that repeatedly cycling, i.e., switching between the two states, can induce stress on the gate dielectric layering FinFET . The stressed transition metal oxide (TMO) layer in the FIND RRAM cells has a stronger tendency to show RTN noises, leading to time-variant read current which can cause read error and stability challenges during data read out. In this experiment, we sampled the read currents of the array at fresh, after 10× cycles and after 100× cycles, in order to observe the stress effect on RTN in the FIND RRAM.
To investigate the temperature effect on stressed FIND RRAM cells, samples with distinct RTN signals in LRS are first cooled down to 0 °C, then, gradually heated it up to 50 °C. During this process, read currents at these temperatures are sampled continuously for 20 s as a rate of 500 Hz. This gives us some clue as to how RTN behave under temperature change.
Results and Discussion
In this paper, the stress and temperature effect on RTN in FIND RRAM cell array is discussed. Cycling stress-induced RTN increase is observed. Effect of high-temperature treatment on reducing RTN and relieving stress for TMO in a FIND RRAM is observed. Finally, an on-chip annealing scheme is proposed and demonstrated.
The authors would like to thank the support from the Ministry of Science and Technology (MOST).
This study is supported by the Ministry of Science and Technology (MOST) and the internal funding of the department.
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Equal contributions for all authors and discussed the results. All authors read and approved the final manuscript.
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