Nanoscale Research Letters

, 13:321 | Cite as

Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor

  • Shupeng Chen
  • Hongxia Liu
  • Shulong Wang
  • Wei Li
  • Xing Wang
  • Lu Zhao
Open Access
Nano Express


In this paper, a silicon-based T-shape gate dual-source tunnel field-effect transistor (TGTFET) is proposed and investigated by TCAD simulation. As a contrastive study, the structure, characteristic, and analog/RF performance of TGTFET, LTFET, and UTFET are discussed. The gate overlap introduced by T-shape gate can enhance the efficiency of tunneling junction. The dual-source regions in TGTFET can increase the on-state current (ION) by offering a doubled tunneling junction area. In order to further improve the device performance, the n+ pocket is introduced in TGTFET to further increase the band-to-band tunneling rate. Simulation results reveal that the TGTFET’s ION and switching ratio (ION/IOFF) reach 81 μA/μm and 6.7 × 1010 at 1 V gate to source voltage (Vg). The average subthreshold swing of TGTFET (SSavg, from 0 to 0.5 V Vg) reaches 51.5 mV/dec, and the minimum subthreshold swing of TGTFET (SSmin, at 0.1 V Vg) reaches 24.4 mV/dec. Moreover, it is found that TGTFET have strong robustness on drain-induced barrier lowering (DIBL) effect. The effects of doping concentration, geometric dimension, and applied voltage on device performance are investigated in order to create the TGTFET design guideline. Furthermore, the transconductance (gm), output conductance (gds), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), and gain bandwidth (GBW) of TGTFET reach 232 μS/μm, 214 μS/μm, 0.7 fF/μm, 3.7 fF/μm, 11.9 GHz, and 2.3 GHz at 0.5 V drain to source voltage (Vd), respectively. Benefiting from the structural advantage, TGTFET obtains better DC/AC characteristics compared to UTFET and LTFET. In conclusion, the considerable good performance makes TGTFET turn into a very attractive choice for the next generation of low-power and analog/RF applications.


T-shaped gate Recessed gate Tunnel field-effect transistor (TFET) Analog/RF performance 



Gate to drain capacitance


Gate to source capacitance


Cut-off frequency


Gain bandwidth


Output conductance




Height of the channel layer


Height of the gate electrode


Height of the source layer


L-shape gate tunnel field-effect transistor


Doping concentration of n+ drain


Doping concentration of n+ pocket


Doping concentration of p+ source


Doping concentration of p− substrate


Output impedance


T-shape gate dual-source tunnel field-effect transistor


Thickness of the HfO2 gate dielectric


Thickness of n+ pocket


U-shape gate tunnel field-effect transistor


Drain to source voltage


Gate to source voltage


Width of the gate electrode


The scaling down of metal-oxide-semiconductor field-effect transistors (MOSFETs) brings significant improvement in integrated circuit (IC) power consumption, switching characteristic, circuit function, and IC density [1, 2]. But the irreconcilable contradiction between the scaling of the supply voltage and the reduction of the off-state leakage currents (IOFF) will finally result in the unacceptable high power consumption [3]. At the same time, reliability degradation caused by short-channel effects (SCEs) becomes more and more serious [4, 5]. In order to address these problems, it is valid to reduce subthreshold swing (SS) and supply voltage of the devices. Based on the band-to-band tunneling mechanism, tunnel field-effect transistors (TFETs) reach the subthreshold swing (SS) smaller than 60 mV/dec and could effectively reduce the supply voltage [6, 7, 8, 9, 10]. Moreover, due to the existence of the tunneling junction near the source, TFET usually has a small gate to source capacitance (Cgs) [1, 11] which is beneficial to the device frequency performance.

Recent studies show that TFET seems to be a promising candidate for future low-power applications [12, 13, 14, 15, 16] and analog/RF applications [17, 18, 19]. However, due to the small effective tunneling area, the limited tunneling current becomes an inherent disadvantage in conventional P-I-N TFET, which leads to a low on-state operating current (ION). In order to improve the TFET performance, many new structures have been proposed in recent years [20, 21, 22, 23, 24, 25]. Benefiting from the recessed gate, L-shape tunnel field-effect transistor (LTFET) [23, 24] and U-shape tunnel field-effect transistor (UTFET) [25] have been proposed to obtain high ION with a compact device structure. However, there is still much room for improvement in LTFET and UTFET and needs to spend more effort to study the analog/RF performance of these devices.

In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with dual source is put forward and studied by TCAD simulation. The designed TGTFET can double the tunneling junction area compared with LTFET and UTFET. The gate overlap introduced by the designed T-shape gate can enhance the band-to-band tunneling rate (BBT rate). The simulation results show that the proposed TGTFET gains a higher ION (8.1 × 10− 5 A/μm at Vd = 1 V) than the LTFET and UTFET under the same condition. Both of the SSmin (at Vg = 0.1 V) and the SSavg (0~0.5 V Vg) of TGTFET are lower than 60 mV/dec (24.4 mV/dec and 51.5 mV/dec, respectively). TGTFET gains better input/output characteristic (gm = 232 μS/μm, gds = 214 μS/μm) than the UTFET and LTFET. Moreover, the capacitance characteristics of TGTFET, UTFET, and LTFET are discussed in detail. Finally, TGTFET gains better analog/RF performance (fT = 11.9 GHz and GBW = 2.3 GHz) compared to UTFET and LTFET. As a result, TGTFET with considerable good performance can be obtained.The structures of this paper are as follows: the “Methods” section includes the description of the structure and the parameters of TGTFET, LTFET [23, 24], and UTFET [25] as well as the TCAD simulation methods. The “Results and Discussion” section includes the description of the simulation results. In this section, the mechanism, characteristic, and analog/RF performance of TGTFET are studied and compared with the LTFET and UTFET. The influence of the device parameters on TGTFET is analyzed in detail too. The “Conclusions” section gives a conclusion of this paper.


The structure of T-shape gate dual-source tunnel field-effect transistor (TGTFET) is illustrated in Fig. 1. The shape of the gate is similar to the alphabet letter “T” (green region). The dual-source regions are located on two sides of the gate (sapphire regions). Two n+ pockets (yellow regions) are inserted to increase the channel tunneling rate [20, 21, 22]. The n+ drain is placed in the bottom of the channel. Therefore, the T-shaped gate overlaps the n+ pockets in both the vertical and lateral directions. By this way, the electric field at the top of the tunneling junction can be increased. The electric field enhancement causes the energy band to bend more steeply. Finally, the electron tunneling rate is enhanced due to the corner electric field enhancement [26].
Fig. 1

Schematic of the proposed T-shape gate dual-source tunnel field-effect transistor (TGTFET)

Figure 2 shows the device structure of LTFET [23, 24], UTFET [25], and TGTFET. The gate overlap can help to enhance the tunneling efficiency of TGTFET. The dual-source regions in TGTFET can double the tunneling junction area compared with LTFET and UTFET.
Fig. 2

Comparison of a the proposed TGTFET, b UTFET, and c LTFET

Parameters of silicon-based TGTFET, UTFET, and LTFET used in simulations are as follows: Hs = 30 nm (height of the source region), Hg = 40 nm (height of the recessed gate), Wg = 6 nm (width of the gate region), Hc = 15 nm (height of the channel region), Tp = 5 nm (thickness of the n+ pocket), ϕ = 4.33 eV (gate work function), Tox = 2 nm (thickness of the HfO2 gate dielectric), NS = 1 × 1020 cm−3 (p+ source doping concentration), ND = 1 × 1019 cm−3 (n+ drain doping concentration), Nsub = 1 × 1017 cm−3 (p− substrate doping concentration), and NP = 5 × 1018 cm−3 (n+ pocket doping concentration). The width coefficient in simulation is default to 1 μm.

Simulations of TGTFET, UTFET, and LTFET are carried out in Silvaco Atlas TCAD tools. Non-local BTBT model is introduced in this simulation to bring the energy band spatial variation into account, which can help to facilitate the accuracy of the BTBT tunneling process. Lombardi mobility model is considered to make the channel mobility more accurate (by considering the surface scattering including the transverse field and doping concentration). Fermi statistics and band gap narrowing model is taken into account to fit the effect of the highly doped regions. Shockley-Read-Hall recombination model is taken into account in this paper, too.

Results and Discussion

Device Mechanism and DC Characteristics with Different Parameters

Figure 3a shows the transfer characteristics of the TGTFET with and without the gate overlap. With the additional gate overlap, the ION increases from 7.5 × 10−5 to 8.1 × 10−5 A/μm at Vg = Vd = 1 V. Figure 3b shows the transfer characteristic curves of TGTFET, UTFET, and LTFET. In order to make the comparison more accurate, the simulation models and geometric dimensions of these three devices are set to be identical. As a result, the TGTFET has about a twofold increase in ION compared with LTFET and UTFET, as shown in Fig. 3b. SSmin of TGTFET is 24.4 mV/dec at Vg = 0.1 V, and SSavg is 51.5 mV/dec when 0 V < Vg < 0.5 V. The switching ratios (ION/IOFF) are 6.7 × 1010 at Vg = Vd = 1 V and 6.5 × 108 at Vg = Vd = 0.5 V.
Fig. 3

Simulated a transfer characteristics of TGTFET with/without gate overlap and b transfer characteristics of TGTFET, UTFET, and LTFET

Figure 4a, b shows the BBT rate of TGTFET with and without a 5-nm gate overlap. From Fig. 4c, we can clearly see that the device with a 5-nm gate overlap has a wider electron tunneling area under the device surface, which can lead to the ION increasing.
Fig. 4

Simulated BBT electron tunneling rate diagrams of a device without gate overlap, b device with 5-nm gate overlap, and c the BBT electron tunneling rate of two devices, at 1 nm below the device surface; Vg = Vd = 1 V

Figure 5a, b shows the 3D diagram of electric fields of TGTFET with and without gate overlap. Two electric field peaks appear in TGTFET with a 5-nm gate overlap, as shown in the dashed circle in Fig. 5a. No electric field peak appears in Fig. 5b attributed to the absences of the gate overlap. Figure 5c shows the energy band structure under the surface of the device. The inset in Fig. 5c shows the cut line location. With the gate overlap, a larger tunneling window can be obtained. Thus, a higher BBT rate and ION can be achieved.
Fig. 5

3D schematic diagram of electric fields of the device a with overlap and b without overlap; simulated c energy band diagrams from source to pocket region (1 nm below the oxide interface)

Figure 6 shows the effects of n+ pocket on the performance of the TGTFET. The IOFF increases rapidly with the increasing of the n+ pocket doping concentration, as shown in Fig. 6a. The lower SS and greater ION can be obtained by decreasing the thickness of n+ pocket (Tp) from 7 to 3 nm when NP = 5 × 1018 cm−3, as shown in Fig. 6b. At the same time, no significant subthreshold current is noted in Fig. 6b. It can be confirmed from Fig. 6a that a relatively low doping concentration of n+ pocket will help to suppress the subthreshold current.
Fig. 6

Simulated drain currents with different n+ pocket a concentrations and b thicknesses at Vd = 1 V

The impact of the gate height (Hg) and channel thickness (Hc) is shown in Fig. 7a, b, separately. A small ION and SS improvement appears when Hg is increasing. Because when Hg = 35 nm, there is an obvious energy band hump on the on-state current path, becoming a certain obstacle to the lucky electrons (electrons which passed the tunneling junction), as shown in Fig. 7c, which can result in Ion decrease. When Hg increases, the energy band hump is weakened, which cause the ION and SS improvement. A slight ION improvement is obtained with Hc decreasing, as shown in Fig. 7b. However, severe degradation on subthreshold characteristic can be observed when Hc decreases to 5 nm. This can be explained by the increasing subthreshold tunneling current at the corner of the n+ pocket, as shown in Fig. 8. Figure 8a shows the obvious off-state band-to-band tunneling phenomenon when Hc = 5 nm while Fig. 8b shows the IOFF current density when Hc = 5 nm.
Fig. 7

Simulated transfer characteristics of TGTFET with a different Hg, b different Hc, and c the conduction band hump on the current path

Fig. 8

Simulated diagrams of off-state a BTBT electron tunneling rate and b current density when Hc = 5 nm

As shown in Fig. 9, the influence of drain to source voltage (Vd) is also taken into account in this paper. For Vd < 0.6 V, ION increases obviously with the increasing Vd, as shown in Fig. 9a. This is explained by the fact that the potential of the p-channel is slowly growing in response to the increasing Vd and results in the decreasing resistance of p-channel. For Vd > 1.8 V, shown in Fig. 9b, the ION almost does not increase with the increasing Vd, but IOFF increases considerably. This is because of the subthreshold tunneling current at the corner of the n+ pocket increasing rapidly with the increasing Vd. Finally, for 0.6 V < Vd < 1.8 V, TGTFET exhibits good and stable performance. As a result, TGTFET is robust to drain-induced barrier lowering (DIBL) and exhibits a good and stable performance in a larger applied voltage dynamic range.
Fig. 9

Simulated drain currents for a Vd ≤ 1 V and b Vd ≥ 1 V

Analog/RF Performance of TGTFET, UTFET, and LTFET

Figure 10 shows the transfer characteristics and transconductance curves of TGTFET, UTFET, and LTFET at Vd = 0.5 V. The transconductance (gm) can be obtained from the first derivative of the transfer characteristic curve, as shown in Eq. (1) [27, 28, 29]:
$$ {g}_{\mathrm{m}}={dI}_{\mathrm{d}s}/{dV}_{\mathrm{gs}} $$
Fig. 10

a Transfer characteristics and b transconductance curves of TGTFET, UTFET, and LTFET at Vd = 0.5 V

As a result, the maximum transconductance of TGTFET (232 μS/μm) is about two times larger than that of UTFET (120 μS/μm) and LTFET (110 μS/μm), as shown in Fig. 10. This is benefited from the current gain contributed by dual source and gate overlap.

Figure 11 shows the output characteristics, output conductance (gds), and output impedance (Ro) curves of the TGTFET, UTFET, and LTFET. As shown in Fig. 11a, it can be clearly seen that the output current of the device increases with the increase of Vd, but when Vd reaches above 0.6 V, the output current tends to saturate. Through observation, it is easy to find that the output current of TGTFET is two times larger than that of UTFET and LTFET. Figure 11b shows the output conductance (gds) and output impedance (Ro) curves of the TGTFET, UTFET, and LTFET. The gds can be obtained through the derivation of the output current, as shown in Eq. (2) [27, 29] while Ro can be expressed as the reciprocal of the output conductance.
$$ {g}_{\mathrm{ds}}={dI}_{\mathrm{ds}}/{dV}_{\mathrm{ds}} $$
Fig. 11

a Output characteristics, b output conductance (gds), and c output impedance (Ro) curves of the TGTFET, UTFET, and LTFET

Due to the advantages on output current, TGTFET gains the highest gds and the minimum Ro of these three devices. Under 1-V gate bias condition, TGTFET obtained the maximum gds of 214 μS/μm and the minimum Ro of 4.6 kΩ/μm under 0.45 V Vd. Under the same gate bias condition, UTFET and LTFET obtained the maximum gds of 113 μS/μm and 105 μS/μm and the minimum Ro of 9.0 kΩ/μm and 9.6 kΩ/μm under 0.4 V Vd.

Moreover, in Fig. 11, it is not difficult to find out that the linear region of the device output characteristics shows certain nonlinearity. As shown in Fig. 11a, Ro decreases first and then increases with the increasing Vd. Some research groups give the corresponding physical process about this phenomenon [7, 30] but there are still some problems that have not been explained clearly. As we know, Ro is determined by the resistance of channel region and tunneling junction. When Vd < 0.4 V, Ro decreases with the increasing Vd. Consider the following situations, when Vd = 0 V and Vg = 1 V, none of the lucky electrons can be swept to the drain side, and almost all the electrons are trapped in the channel region by a relatively high drain barrier, as shown in the red dotted line frame in Fig. 12a, b. When 0 V < Vd < 0.4 V, with the increasing of Vd, the drain barrier becomes weaker (as shown in Fig. 12b). Thus, the electrons trapped in the channel region can pass through the drain barrier and then be collected by drain. This is a thermal excitation process of electrons from channel to drain. Finally, as the tunneling junction has been completely turned on (when Vg = 1 V), the tunneling current is always in a state of excess and the resistance introduced by tunneling junction can be ignored. At this time, Ro is determined by the channel resistance and Ro is decided by the electron thermal excitation process across the drain barrier. Thus, Ro decreases with the increasing of Vd. When Vd > 0.6 V, these three devices gradually enter the saturation area and Ro becomes larger. This is because when Vd is large, almost all the electrons through the tunneling junction are swept to the drain side by the relatively high electric field. The tunneling current becomes the limit of the drain current. In this condition, Ro is mainly determined by the tunneling junction. However, the tunneling efficiency cannot increase significantly while Vd is increasing. Vd has a small effect on the energy band structure of the tunneling junction (n+ pocket side), as shown in Fig. 12b. As a result, the tunneling current cannot increase obviously, and there is almost no ION increase with the continually increasing Vd (when Vd > 0.6 V), which means an impedance increases. Moreover, when 0.4 V < Vd < 0.6 V, Ro is determined by both the channel resistance and tunneling junction.
Fig. 12

a Schematic diagram of the energy band at Vd = 0 V and Vg = 1 V. b Simulation results of the energy band diagram at different biases of Vd

It can be obtained from the above analysis that the Ro of TFET is influenced by both the tunneling process and the channel electron thermal excitation process. The main physical mechanisms can dominate Ro shifts with Vd variation. Finally, the Ro decreases first and then increases, thus causing the nonlinearity of the output characteristics. Incidentally, through the observation of Fig. 11b, it is easy to find that the output impedance of TGTFET is much smaller than that of the UTFET and LTFET. This is due to the better tunneling efficiency benefit from the dual-source and the lateral gate overlap structure of TGTFET.

Figure 13 shows the energy band structure of TGTFET, UTFET, and LTFET with different applied voltages. The red dotted lines in the inset represent the position to draw the energy band (which is 15 nm below the surface, just at the 1/2 height of the source region). It can be seen that with a Vd increase from 0.1 to 0.5 V, the band structure of TGTFET, UTFET, and LTFET has an obvious trend of bending. This is because the drain voltage can pull down the electric potential of the tunneling junction near the drain side. This indicates that, for TGTFET, UTFET, and LTFET, the increase of Vd from 0.1 to 0.5 V is beneficial to tunneling efficiency. However, when Vd > 0.5 V, the change of the energy band with Vd increase is not worth mentioning. This is consistent with the analysis results in Fig. 12b.
Fig. 13

The energy band structure of a TGTFET, b UTFET, and c LTFET at Vg = 1

As we know, the gate capacitance (Cgg) of the device can greatly affect the frequency characteristics of the integrated circuits. For TGTFET, UTFET, and LTFET, Cgg generally consists of Cgs (capacitance of gate to source) and Cgd (gate to drain capacitance). Therefore, the characteristic of Cgg, Cgs, and Cgd is of great significance to evaluate the frequency characteristics and analog application ability of devices. Especially for TFET, the capacitance characteristics are quite different from MOSFET. Because of the existence of the tunneling junction at the source area, TFET usually has a small Cgs [1, 11]. Therefore, the Cgg of TFET is mainly determined by Cgd. Figure 14 shows the capacitance of TGTFET, UTFET, and LTFET versus Vg under Vd = 0.5 V and Vd = 0 V, separately.
Fig. 14

Capacitance of TGTFET versus Vg under a Vd = 0 V and b Vd = 0.5 V. Capacitance of UTFET versus Vg under c Vd = 0 V and d Vd = 0.5 V. Capacitance of LTFET versus Vg under e Vd = 0 V and f Vd = 0.5 V

Through the observation of Fig. 14a, b, it is easy to find that the Cgs of TGTFET under 1-V gate voltage is 0.15 fF/μm at Vd = 0 V and 0.7 fF/μm at Vd = 0.5 V, which is far more smaller than that of the Cgd (5.8 fF/μm at Vd = 0 V and 3.7 fF/μm at Vd = 0.5 V). Thus, the Cgg of TGTFET is mainly determined by Cgd. When Vd = 0 V, Cgg and Cgd increase rapidly with the increasing Vg, as shown in Fig. 14a. This is because with the increase of Vg, electrons are aggregated to the gate interface in the device channel, which makes the capacitance rise rapidly. When Vd = 0.5 V, Cgd does not increase obviously until Vg is increased to more than 0.6 V, as shown in Fig. 14b. This is because when Vg is low, only few lucky electrons can pass through the tunneling junction and go into the channel. Some of these lucky electrons will be participating in the recombination process, and most of the others will be rapidly collected by drain due to the 0.5-V drain voltage. Therefore, it is very difficult for these lucky electrons to stay in the device channel. However, with the Vg increase, the number of lucky electrons increases rapidly. At this moment, neither of the drain collection nor of the electron-hole recombination process can rapidly deplete these lucky electrons. Thus, the electron concentration in the channel increases and the capacitance rises rapidly. As a result, the capacitance characteristic curve tends to shift right while Vd increases, as shown in Fig. 14a, b. The above analysis and phenomena are also applicable to UTFET and LTFET, as shown in Fig. 14cf. In addition, the gate capacitance of UTFET at 0 V and 0.5 V Vd reached 6.2 fF/μm and 5.1 fF/μm, respectively, and that of the LTFET reached 3.4 fF/μm and 2.7 fF/μm, respectively.

Since there is no direct overlap between the LTFET’s gate and drain, and the distance between the gate and drain is relatively far, LTFET has the best capacitance characteristics and the smallest Cgg. In contrast, there is a direct overlap between the UTFET’s gate and drain. Therefore, electrons near the drain side are more easily controlled by gate, thus resulting in a large Cgg of UTFET. For TGTFET, although the distance between the gate and drain is close, but there is a lightly doped channel region which can isolate the gate and drain. Thus, the capacitance of TGTFET is better than that of the UTFET, but slightly inferior to LTFET. Figure 15 shows the Cgd characteristics of TGTFET, UTFET, and LTFET versus Vd under different Vg. From the observation of Fig. 15av, it is not difficult to find that the Cgd characteristics of these three devices are similar. That is, for a fixed Vg, Cgd decreases with the increase of the Vd. On the other hand, for a fixed Vd, Cgd increases with the increase of Vg.
Fig. 15

Cgd characteristics of a TGTFET, b UTFET, and c LTFET versus Vd under different Vg

As we know, both of the cut-off frequency (fT) and gain bandwidth (GBW) are the evaluation criteria for evaluating the frequency characteristics of devices. fT depends on the ratio of gm to Cgg, as shown in Eq. (3) [30, 31]. For a certain DC gain that equals 10, GBW can be expressed by the ratio of gm to Cgd, as shown in Eq. (4) [17]:
$$ {f}_T=\frac{g_{\mathrm{m}}}{2\pi {C}_{\mathrm{gs}}\sqrt{1+2{C}_{\mathrm{gd}}/{C}_{\mathrm{gs}}}}\approx \frac{g_{\mathrm{m}}}{2\pi \left({C}_{\mathrm{gs}}+{C}_{\mathrm{gd}}\right)}=\frac{g_{\mathrm{m}}}{2\pi {C}_{\mathrm{gg}}} $$
$$ \mathrm{GWB}={g}_{\mathrm{m}}/2\pi 10{C}_{\mathrm{gd}} $$
Figure 16 shows the characteristic curves of the fT and GBW of TGTFET, UTFET, and LTFET. Benefiting from structural advantages, such as dual-source and lateral gate overlap introduced by the T-shaped gate, TGTFET obtains the most outstanding frequency characteristics compared with UTFET and LTFET. Under the condition of Vd = 0.5 V, the fT and GBW of TGTFET reached the maximum values of 11.9 GHz and 2.3 GHz, respectively. Benefiting from the long distance between gate and drain and without gate/drain overlap, LTFET obtains a small Cgg and good frequency characteristics. The fT and GBW of LTFET reach the 8.7 GHz and 2.1 GHz, separately. The capacitance characteristics of UTFET are inferior compared with that of TGTFET and LTFET. This is because the direct gate/drain overlaps. As a result, the maximum value of fT and GBW of UTFET can only reach 4.1 GHz and 0.5 GHz separately.
Fig. 16

The characteristic curves of a fT and b GBW of TGTFET, UTFET, and LTFET versus Vg at Vd = 0.5 V


In this paper, a T-shape gate dual-source tunnel field-effect transistor (TGTFET) with good performance is proposed and investigated. The structure, mechanism, and the influence of device parameter on the characteristic of TGTFET are discussed. In addition, the characteristics of TGTFET, UTFET, and LTFET are discussed and compared in this paper. The dual-source regions are introduced to double the area of the tunneling junction. The gate overlap and the n+ pockets can obviously enhance the tunneling efficiency of the tunneling junction in TGTFET. Finally, the TGTFET with impressive characteristics (ION = 8.1 × 10−5 A/μm, ION/IOFF = 6.7 × 1010 and SSmin = 24.4 mV/dec) is obtained. At the same time, TGTFET is robust to DIBL, which means TGTFET can exhibit a good and stable performance in a larger applied voltage dynamic range. Furthermore, the analog/RF performance of TGTFET is studied and compared with UTFET and LTFET. The key parameter such as input/output characteristics, capacitance characteristics, GBW, and fT are analyzed. Benefiting from the no direct overlap between the gate and drain, TGTFET obtains a relatively small Cgd and Cgg. Finally, TGTFET with remarkable frequency characteristics (fT = 11.9 GHz and GBW = 2.3 GHz) is obtained. As a conclusion, it is expected that TGTFET can be one of the promising alternatives for the next generation of device in low-power and analog/RF applications.



In particular, we thank Dr. Wenxing Tian for the discussion and help in the process of writing this manuscript.


This research is supported by the National Natural Science Foundation of China (Grant Nos. 61434007 and 61504100), the Foundation for Fundamental Research of China (Grant No. JSZL2016110B003), and the Major Fundamental Research Program of Shaanxi (Grant No. 2017ZDJC-26).

Authors’ Contributions

SC puts forward the innovative results in this manuscript and completed the work of simulation and article writing. HL and SW supported the completion of this work and helped in the format modification and detail discussion. WL, XW, and LZ participated in the format modification and detail discussion. All authors read and approved the final manuscript.

Authors’ Information

Shupeng Chen was born in 1987. He received his B.S., M.S., and Ph.D degrees in Microelectronics from Xidian University in 2010, 2013, and 2017, respectively. He joined Xidian University in 2018. His current research interests include advanced CMOS device designs and steep-switching device designs. Hongxia Liu was born in 1968. She received her B.S., M.S., and Ph.D degrees in Microelectronics from North West University, Xi’an Jiaotong University, and Xidian University, Xi’an, China, in 1990, 1995, and 2002, respectively. She has been a professor of Microelectronics, Xidian University since 2002. Her current research interests include advanced CMOS and ultralow power device designs and reliability. Shulong Wang was born in 1983. He received his B.S. in Electronic Information Science and Technology from Xidian University in 2006 and received his M.S. and Ph.D degrees in electronic science and technology from Xidian University in 2009 and 2014, respectively. He joined Xidian University in 2014. His current research interests include advanced CMOS device designs and their applications to ultralow power integrated circuit. Wei Li was awarded a BS degree from the School of Electrical Engineering at Tianjin University of Technology, Tianjin, China, in 2014. He attended the Xidian University from 2014 to 2015. Since 2017, he has been working toward the Ph.D degree in advance at the School of Microelectronics. Xing Wang was born in 1991. He received Ph.D degree in Microelectronics from Xidian University in 2017. He joined Xidian University in 2017. His current research interests include high-k materials and advanced CMOS device designs. Lu Zhao was born in 1992. She received his B.S. degree in Microelectronics from Xidian University in 2014. She is currently working toward her Ph.D degree in Microelectronics from Xidian University. Her current research interests include high-k materials and advanced Ge-based CMOS device designs and fabrications.

Competing Interests

The authors declare that they have no competing interests.

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  1. 1.
    Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature.
  2. 2.
    V. Vijayvargiya and S. K. Vishvakarma. Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Transactions on Nanotechnology. 2014; doi:
  3. 3.
    D. Kim, Y. Lee and J. Cai et al. Low power circuit design based on heterojunction tunneling transistors (HETTs). IEEE ISLPED 2009; doi:
  4. 4.
    Hiblot G. et al. Accurate boundary condition for short-channel effect compact modeling in MOS devices. IEEE Transactions on Electron Devices 2015; doi:
  5. 5.
    S. Bangsaruntip, G. M. Cohen, A. Majumdar et al. Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Electron Device Lett 2010; doi:
  6. 6.
    J. Madan and R. Chaujar. Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance superlattices and microstructures 2017; doi:
  7. 7.
    G. Singh, S. I. Amin and S. Anand et al. Design of Si 0.5 Ge 0.5 based tunnel field effect transistor and its performance evaluation. Superlattices & Microstructures. 2016; doi:
  8. 8.
    Q. Huang, R. Huang and Z. Zhan et al. A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration. IEEE IEDM 2012; doi:
  9. 9.
    U. E. Avci and I. A. Young. Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length. IEEE IEDM. 2013; doi:
  10. 10.
    W. Y. Choi, B. G. Park and J. D. Lee et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 2007; doi:
  11. 11.
    Appenzeller J., Lin Y. M., Knoch J. et al. Comparing carbon nanotube transistors - the ideal choice: a novel tunneling device design. IEEE Trans. Electron Devices. 2005; doi:
  12. 12.
    A. Villalon, G. L. Carval and S. Martinie et al. Further insights in TFET operation. IEEE Trans. Electron Devices. 2014; doi:
  13. 13.
    V. Nagavarapu, R. Jhaveri and J. C. S. Woo. The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans. Electron Devices. 2008; doi:
  14. 14.
    N. Gupta, A. Makosiej and C. Anghel et al. Ultra-low-power compact TFET flip-flop design for high-performance low-voltage applications IEEE ISQED 2016; doi:
  15. 15.
    N. Gupta, A. Makosiej and A. Vladimirescu et al. 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applications. DATE .2016; doi:
  16. 16.
    Chen S, Wang S, Liu H, et al. Symmetric U-shaped gate tunnel field-effect transistor. IEEE Transactions on Electron Devices. 2017; doi:
  17. 17.
    Chen S, Liu H, Wang S, et al. Analog/RF performance of two tunnel FETs with symmetric structures. Superlattices & Microstructures 2017; doi:
  18. 18.
    Li W, Liu H, Wang S, et al. Reduced miller capacitance in U-shaped channel tunneling FET by introducing heterogeneous gate dielectric. IEEE Electron Device Lett 2017; doi:
  19. 19.
    Wang Q, Wang S, Liu H et al (2017) Analog/RF performance of L- and U-shaped channel tunneling field-effect transistors and their application as digital inverters. Jpn J Appl Phys.
  20. 20.
    D. B. Abdi and M. J. Kumar. In-built N+ pocket p-n-p-n tunnel field-effect transistor. IEEE Electron Device Lett. 2014; doi:
  21. 21.
    W. Cao, C. J. Yao and G. F. Jiao et al. Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure. IEEE Trans. Electron Devices. 2011; doi:
  22. 22.
    A. Mallik, A. Chattopadhyay and S. Guin et al. Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices 2013; doi:
  23. 23.
    Kim SW, Choi WY, Sun MC et al (2012) Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn J Appl Phys.
  24. 24.
    S. W. Kim, J. H. Kim and T. J. K. Liu et al. Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans. Electron Devices. 2016; doi:
  25. 25.
    W. Wang, P. F. Wang and C. M. Zhang et al. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans. Electron Devices. 2014; doi:
  26. 26.
    Y. Morita, T. Mori and S. Migita et al. Performance enhancement of tunnel field-effect transistors by synthetic electric field effect, IEEE Electron Device Lett. 2014; doi:
  27. 27.
    Boucart K, Ionescu AM (2007) Length scaling of the double gate tunnel FET with a high-k gate dielectric. Solid State Electron.
  28. 28.
    Narang R, Saxena M, GuptaR S, et al. Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack. International Journal of VLSI Design & Communication Systems (VLSICS) 2011; doi:
  29. 29.
    Gupta S K, Baishya S. Analog and RF performance evaluation of dual metal double gate high-k stack (DMDG-HKS) MOSFETs. J Nano Electron Phys. 2013; Available: search/index.php?option=com_content&task=full_article&id=984
  30. 30.
    Akram M. W., B. Ghosh. Analog performance of double gate junctionless tunnel field effect transistor. Journal of Semiconductors. 2014; doi:
  31. 31.
    Mohankumar N, Syamal B, Sarkar CK (2009) Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications. Microelectron Rel.

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Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors and Affiliations

  1. 1.School of Microelectronics, Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of EducationXidian UniversityXi’anChina

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