Abstract
We propose novel hardware accelerator architectures for the most computationally demanding algorithms of the MPEG-4 video compression standard-motion estimation, binary motion estimation (for shape coding), and the forward/inverse discrete cosine transforms (incorporating shape adaptive modes). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09 μ m TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art.
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Kinane, A., Larkin, D. & O'Connor, N. Energy-Efficient Acceleration of MPEG-4 Compression Tools. J Embedded Systems 2007, 028735 (2007). https://doi.org/10.1155/2007/28735
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DOI: https://doi.org/10.1155/2007/28735