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Sklansky tree adder realization in 1S1R resistive switching memory architecture

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Abstract

Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed.

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Authors and Affiliations

  1. Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074, Aachen, Germany

    Anne Siemon, Rainer Waser & Eike Linn

  2. JARA – Fundamentals for Future Information Technology, 52425, Jülich, Germany

    Anne Siemon, Stephan Menzel, Rainer Waser & Eike Linn

  3. Peter Grünberg Institut 7 (PGI-7), Forschungszentrum Jülich GmbH, 52425, Jülich, Germany

    Stephan Menzel & Rainer Waser

  4. School of Computer Science and Engineering, Nanyang Technological University, 639798, Singapore, Singapore

    Debjyoti Bhattacharjee & Anupam Chattopadhyay

Authors
  1. Anne Siemon
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  2. Stephan Menzel
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  3. Debjyoti Bhattacharjee
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  4. Rainer Waser
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  5. Anupam Chattopadhyay
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  6. Eike Linn
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Correspondence to Anne Siemon.

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Siemon, A., Menzel, S., Bhattacharjee, D. et al. Sklansky tree adder realization in 1S1R resistive switching memory architecture. Eur. Phys. J. Spec. Top. 228, 2269–2285 (2019). https://doi.org/10.1140/epjst/e2019-900042-x

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  • DOI: https://doi.org/10.1140/epjst/e2019-900042-x

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