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A capacitance model for threshold voltage computation of double-insulating fully-depleted silicon-on-diamond MOSFET

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Abstract

In this paper, we present a capacitance model for 22 nm double-insulating (DI) fully-depleted (FD) silicon-on-diamond (SOD) MOSFET near the threshold voltage. The model takes into account the capacitance coupling between the front- and back-gate to the source/drain layers through the diamond layer, the second insulating layer (SiO2), and the substrate. The second insulating layer is located on top and partially covers the diamond layer, serving to enhance device electrostatics and enable a heat spreading mechanism from the device’s active region through the diamond layer. The effects of substrate depletion capacitance and the length and thickness of the second insulating layer are incorporated into the model as corresponding capacitances. Surface potentials in the silicon layer of the transistor are calculated, and a strong inversion condition is applied. Using the capacitance model, we compute the front- and back-gate threshold voltages and compare them with those obtained from TCAD simulations. The results from the analytical solutions and device simulations are promising, exhibiting good agreement in terms of gate oxide thickness, silicon film thickness, buried diamond layer thickness, second insulating layer thickness, and length. We observe an 8 mV variation in the front-gate threshold voltage and a 20 mV difference in the back-gate threshold voltage when the length of the second insulating layer is changed from 22 to 102 nm, considering a silicon film thickness of 5 nm. For a second insulating layer length smaller than 40 nm, the perpendicular source/drain capacitance to the back body has the most significant influence on the back channel. Conversely, for a second insulating layer length greater than 60 nm, the co-planar source/drain capacitance to the back body dominates. Overall, the capacitance model provides valuable insights into the impact of the second insulating layer length on the threshold voltage of the DI FD SOD MOSFET.

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References

  1. R. Carter, J. Mazurier, L. Pirro, J-U. Sachse, P. Baars, J. Faul1, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P. Y. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H. -J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet, J. Schaeffer, B. Rice, 22 nm FDSOI technology for emerging mobile, internet-of-things, and rf applications, in 2016 IEEE International Electron Devices Meeting (IEDM), 221–224, (2016) https://doi.org/10.1109/IEDM.2016.7838029.

  2. S. Makovejev, N. Planes, M. Haond, D. Flandre, J.P. Raskin, V. Kilchytska, Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI. Solid-State Electron. 115, 219–224 (2016). https://doi.org/10.1016/j.sse.2015.08.022

    Article  ADS  Google Scholar 

  3. ITRS, International Technology Roadmap for Semiconductors 2.0, Semiconductor Industry Association, 2015.

  4. A. Halder, L. Nyssens, M. Rack, D. Lederer, J.P. Raskin, V. Kilchytska, Heat sink implementation in back-end of line for self-heating reduction in 22 nm FDSOI MOSFETs. Solid-State Electron. 184, 108088 (2021). https://doi.org/10.1016/j.sse.2021.108088

    Article  Google Scholar 

  5. J. Ahopelto, G. Ardila, L. Baldi, F. Balestra, D. Belot, G. Fagas, S. De Gendt, D. Demarchi, M. Fernandez-Bolaños, D. Holden, A.M. Ionescu, G. Meneghesso, A. Mocuta, M. Pfeffer, R.M. Popp, E. Sangiorgi, C.M. Sotomayor Torres, NanoElectronics roadmap for Europe: from nanodevices and innovative materials to system integration. Solid-State Electron. 155, 7–19 (2019). https://doi.org/10.1016/j.sse.2019.03.014

    Article  ADS  Google Scholar 

  6. K. Raleva, D. Vasileska, S.M. Goodnick, Is SOD technology the solution to heating problems in SOI devices? IEEE Electron Device Lett. 29(6), 621–624 (2008). https://doi.org/10.1109/LED.2008.920756

    Article  ADS  Google Scholar 

  7. A. Aleksov, J.M. Gobien, X. Li, J.T. Prater, Z. Sitar, Silicon-on-diamond—an engineered substrate for electronic applications. Diam. Relat. Mater. 15(2–3), 248–253 (2006). https://doi.org/10.1016/j.diamond.2005.09.012

    Article  ADS  Google Scholar 

  8. M. Rabarot, J. Widiez, S. Saada, J.-P. Mazellier, C. Lecouvey, J.-C. Roussin, J. Dechamp, P. Bergonzo, F. Andrieu, O. Faynot, S. Deleonibus, L. Clavelier, J.P. Roger, Silicon-on-diamond layer integration by wafer bonding technology. Diam. Relat. Mater. 19(7–9), 796–805 (2010). https://doi.org/10.1016/j.diamond.2010.01.049

    Article  ADS  Google Scholar 

  9. J. Widiez, M. Rabarot, S. Saada, J.P. Mazellier, J. Dechamp, V. Delaye, J.-C. Roussin, F. Andrieu, O. Faynot, S. Deleonibus, P. Bergonzo, L. Clavelier, Fabrication of silicon on diamond (SOD) substrates by either the bonded and etched-back SOI (BESOI) or the Smart-Cut™ technology. Solid-State Electron. 54(2), 158–163 (2010). https://doi.org/10.1016/j.sse.2009.12.012

    Article  ADS  Google Scholar 

  10. J.-P. Mazellier, J. Widiez, F. Andrieu, M. Lions, S. Saada, M. Hasegawa, K. Tsugawa, L. Brevard, J. Dechamp, M. Rabarot, V. Delaye, S. Cristoloveanu, L. Clavelier, S. Deleonibus, P. Bergonzo, O. Faynot, First demonstration of heat dissipation improvement in CMOS technology using Silicon-On-Diamond (SOD) substrates. IEEE Int. SOI Conf. 2009, 1–2 (2009). https://doi.org/10.1109/SOI.2009.5318735

    Article  Google Scholar 

  11. R. Nirosha, R. Agarwal, Characterization and modeling of threshold voltage for organic and amorphous thin-film transistors. Microelectron. Reliabil. (2023). https://doi.org/10.1016/j.microrel.2023.115054

    Article  Google Scholar 

  12. A. Daghighi, Double insulating silicon on diamond device, ed. US Patent 9077588, (2015).

  13. A. Daghighi, A novel structure to improve DIBL in fully-depleted silicon-on-diamond substrate. Diam. Relat. Mater. 40, 51–55 (2013). https://doi.org/10.1016/j.diamond.2013.10.010

    Article  ADS  Google Scholar 

  14. W. Zhu, G. Zheng, S. Cao, H. He, Thermal conductivity of amorphous SiO2 thin film: a molecular dynamics study. Sci. Rep. (2018). https://doi.org/10.1038/s41598-018-28925-6

    Article  Google Scholar 

  15. B. Sviličić, V. Jovanović, T. Suligoj, Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs. Solid-State Electron. 53(5), 540–547 (2009). https://doi.org/10.1016/j.sse.2009.03.002

    Article  ADS  Google Scholar 

  16. DESSIS, ISE Integrated System Engineering, Version 10.0, 2004

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Authors and Affiliations

  1. Faculty of Engineering, Shahrekord University, Shahrekord, Iran

    Arash Daghighi & Afshin Dadkhah

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  1. Arash Daghighi
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  2. Afshin Dadkhah
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Correspondence to Arash Daghighi.

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Daghighi, A., Dadkhah, A. A capacitance model for threshold voltage computation of double-insulating fully-depleted silicon-on-diamond MOSFET. Eur. Phys. J. Plus 138, 1129 (2023). https://doi.org/10.1140/epjp/s13360-023-04758-9

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