Advertisement

The European Physical Journal Special Topics

, Volume 228, Issue 10, pp 2269–2285 | Cite as

Sklansky tree adder realization in 1S1R resistive switching memory architecture

  • Anne SiemonEmail author
  • Stephan Menzel
  • Debjyoti Bhattacharjee
  • Rainer Waser
  • Anupam Chattopadhyay
  • Eike Linn
Regular Article
  • 23 Downloads
Part of the following topical collections:
  1. Memristor-based Systems: Nonlinearity, Dynamics and Applications

Abstract

Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    M.A. Zidan, J.P. Strachan, W.D. Lu, Nat. Electron. 1, 22 (2018)CrossRefGoogle Scholar
  2. 2.
    J.J. Yang, D.B. Strukov, D.R. Stewart, Nat. Nanotechnol. 8, 13 (2013)ADSCrossRefGoogle Scholar
  3. 3.
    W. Kim, S. Menzel, D.J. Wouters, R. Waser, V. Rana, IEEE Electron Device Lett. 37, 564 (2016)ADSCrossRefGoogle Scholar
  4. 4.
    S. Poblador, M. Gonzalez, F. Campabadal, Microelectron. Eng. 187, 148 (2018)CrossRefGoogle Scholar
  5. 5.
    A. Prakash, J. Park, J. Song, J. Woo, E. Cha, H. Hwang, IEEE Electron Device Lett. 36, 32 (2015)ADSCrossRefGoogle Scholar
  6. 6.
    A. Flocke, T.G. Noll, in Proceedings of the 33rd European Solid-State Circuits Conference (2007), p. 328Google Scholar
  7. 7.
    E. Linn, R. Rosezin, C. Kügeler, R. Waser, Nat. Mater. 9, 403 (2010)ADSCrossRefGoogle Scholar
  8. 8.
    G. Burr, R. Shenoy, K. Virwani, P. Narayanan, A. Padilla, B. Kurdi, H. Hwang, J. Vac. Sci. Technol. B 32, 040802 (2014)CrossRefGoogle Scholar
  9. 9.
    E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, R. Waser, Nanotechnology 23, 305205 (2012)CrossRefGoogle Scholar
  10. 10.
    J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, R.S. Williams, Nature 464, 873 (2010)ADSCrossRefGoogle Scholar
  11. 11.
    S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, IEEE Trans. Circuits Syst. Express Briefs 61, 895 (2014)CrossRefGoogle Scholar
  12. 12.
    T. You, Y. Shuai, W. Luo, N. Du, D. Bürger, I. Skorupa, R. Hübner, S. Henker, C. Mayr, R. Schüffny, T. Mikolajick, O.G. Schmidt, H. Schmidt, Adv. Funct. Mater. 24, 3357 (2014)CrossRefGoogle Scholar
  13. 13.
    A. Siemon, T. Breuer, N. Aslam, S. Ferch, W. Kim, J. van den Hurk, V. Rana, S. Hoffmann-Eifert, R. Waser, S. Menzel, E. Linn, Adv. Funct. Mater. 25, 6414 (2015)CrossRefGoogle Scholar
  14. 14.
    E. Lehtonen, M. Laiho, in 2009 IEEE/ACM International Symposium on Nanoscale Architectures, San Francisco, CA, USA, July 30–31 2009 (2009), p. 33Google Scholar
  15. 15.
    S. Kvatinsky, E.G. Friedman, A. Kolodny, U.C. Weiser, IEEE Trans. Very Large Scale Integr. VLSI Syst. 22, 2054 (2014)CrossRefGoogle Scholar
  16. 16.
    A. Siemon, S. Menzel, R. Waser, E. Linn, IEEE J. Emerging. Sel. Top. Circuits Syst. 5, 64 (2015)ADSCrossRefGoogle Scholar
  17. 17.
    N. Talati, S. Gupta, P. Mane, S. Kvatinsky, IEEE Trans. Nanotechnol. 15, 635 (2016)ADSCrossRefGoogle Scholar
  18. 18.
    M. Teimoory, A. Amirsoleimani, J. Shamsi, A. Ahmadi, S. Alirezaee, M. Ahmadi, in 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marseille, France, December 7–10 2014 (2014)Google Scholar
  19. 19.
    M. Le Gallo, A. Sebastian, R. Mathis, M. Manica, H. Giefers, T. Tuma, C. Bekas, A. Curioni, E. Eleftheriou, Nat. Electron. 1, 246 (2018)CrossRefGoogle Scholar
  20. 20.
    T. Breuer, A. Siemon, E. Linn, S. Menzel, R. Waser, V. Rana, Adv. Electron. Mater. 1, 1500138 (2015)CrossRefGoogle Scholar
  21. 21.
    J. Sklansky, IRE Trans. Electron. Comput. (USA) EC-9, 226 (1960)MathSciNetCrossRefGoogle Scholar
  22. 22.
    D. Harris, in Conference Record of the Thirty-Seventh Asilomar Conference On Signals, Systems & Computers (2003), Vols. 1 and 2, p. 2213Google Scholar
  23. 23.
    A. Siemon, S. Menzel, A. Marchewka, Y. Nishi, R. Waser, E. Linn, in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (2014), p. 1420Google Scholar
  24. 24.
    A. Siemon, S. Menzel, A. Chattopadhyay, R. Waser, E. Linn, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015 (2015), p. 13Google Scholar
  25. 25.
    E. Linn, A. Siemon, R. Waser, S. Menzel, IEEE Trans. Circuits Syst. Regul. Pap. (TCAS-I) 61, 2402 (2014)CrossRefGoogle Scholar
  26. 26.
    S. Menzel, A. Siemon, A. Ascoli, R. Tetzlaff, in Proceedings of 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 27–30 May 2018, Florence, Italy (2018)Google Scholar
  27. 27.
    S. Kim, W. Lee, H. Hwang, in 2012 13th International Workshop On Cellular Nanoscale Networks and Their Applications (CNNA) (IEEE, 2012), pp. 1–2Google Scholar
  28. 28.
    D. Bhattacharjee, A. Siemon, E. Linn, S. Menzel, A. Chattopadhyay, ACM JETC 14, 30 (2018)Google Scholar
  29. 29.
    E. Lehtonen, J.H. Poikonen, M. Laiho, Electron. Lett. 46, 239 (2010)CrossRefGoogle Scholar
  30. 30.
    K. Kim, S. Shin, S.M. Kang, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30, 1800 (2011)CrossRefGoogle Scholar
  31. 31.
    J. Reuben, R. Ben-Hur, N. Wald, N. Talati, A.H. Ali, P.-E. Gaillardon, S. Kvatinsky, in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 25–27 September 2017 (2017)Google Scholar
  32. 32.
    P.-E. Gaillardon, L. Amaru, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 14–18 March 2016 (2016), p. 1Google Scholar
  33. 33.
    X. Hu, M.J. Schultis, M. Kramer, A. Bagla, A. Shetty, J.S. Friedman, IEEE Trans. Circuits Syst. Regul. Pap. (TCAS-I) 66, 263 (2018)CrossRefGoogle Scholar

Copyright information

© EDP Sciences, Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Anne Siemon
    • 1
    • 2
    Email author
  • Stephan Menzel
    • 2
    • 3
  • Debjyoti Bhattacharjee
    • 4
  • Rainer Waser
    • 1
    • 2
    • 3
  • Anupam Chattopadhyay
    • 4
  • Eike Linn
    • 1
    • 2
  1. 1.Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen UniversityAachenGermany
  2. 2.JARA – Fundamentals for Future Information TechnologyJülichGermany
  3. 3.Peter Grünberg Institut 7 (PGI-7), Forschungszentrum Jülich GmbHJülichGermany
  4. 4.School of Computer Science and Engineering, Nanyang Technological UniversitySingaporeSingapore

Personalised recommendations