Abstract
The main goal of this paper is to demonstrate that the newest generation of NEC SX-Aurora TSUBASA architecture can perform large-scale graph processing extremely efficiently. This paper proposes approaches, which can be used for the development of high-performance vector-oriented implementations of page rank and shortest paths algorithms, including vectorised graph storage format, efficient vector-friendly graph traversals, optimised cache-aware memory accesses and efficient load-balancing. The developed implementations are optimised according to the most important features and properties of SX-Aurora architecture, which allows them achieve up to 15 times better performance compared to the optimised Intel Skylake parallel implementations and up to 5 times better performance compared to NVGRAPH library implementations for Pascal GPU architecture.
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Funding
This project was partially supported by JSPS Bilateral Joint Research Projects program, entitled “Theory and Practice of Vector Data Processing at Extreme Scale: Back to the Future”. The reported study was supported by the Russian Foundation for Basic Research, project no. 18-57-50005.
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Submitted by E. E. Tyrtyshnikov
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Afanasyev, I.V., Voevodin, V.V., Voevodin, V.V. et al. Developing Efficient Implementations of Shortest Paths and Page Rank Algorithms for NEC SX-Aurora TSUBASA Architecture. Lobachevskii J Math 40, 1753–1762 (2019). https://doi.org/10.1134/S1995080219110039
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DOI: https://doi.org/10.1134/S1995080219110039