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Short Complete Fault Detection Tests for Logic Networks with Fan-In Two

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Abstract

It is established that we can implement almost every Boolean function on n variables by a logic network in the basis {x&y, xy, xy, 1}, allowing a complete fault detection test with length at most 4 under arbitrary stuck-at faults at outputs of gates. The following assertions are also proved:We can implement each Boolean function on n variables by a logic network in the basis {x&y, xy, xy, 1} (in the basis {x&y, xy, xy, x ⨁ y}) containing at most one dummy variable and allowing a complete fault detection test of length at most 5 (at most 4, respectively) under faults of the same type.

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References

  1. S. V. Yablonskii, “Reliability and Monitoring of Control Systems,” in Proceedings of All-Union Seminar on Discrete Mathematics and Its Applications, Moscow, Russia, January 31—February 2, 1984 (Izd. MGU,Moscow, 1986), pp. 7–12.

    Google Scholar 

  2. S. V. Yablonskii, “Certain Questions of Reliability and Monitoring of Control Systems,” in Mathematical Problems of Cybernetics, Vol. 1 (Nauka, Moscow, 1988), pp. 5–25.

    Google Scholar 

  3. N. P. Red’kin, Reliability and Diagnosis of Circuits (Izd.Moskov.Gos. Univ.,Moscow, 1992) [in Russian].

    MATH  Google Scholar 

  4. K. A. Popkov, “Complete Fault Detection Tests of Length 2 for Logic Networks under Stuck-At Faults of Gates,” Diskretn. Anal. Issled. Oper. 25 (2), 62–81 (2018) [J. Appl. Indust. Math. 12 (2), 302–312 (2018)].

    MATH  Google Scholar 

  5. N. P. Red’kin, “On Complete Checking Tests for Circuits of Functional Elements,” Vestnik Moskov. Univ. Ser. 1:Mat.Mekh. No. 1, 72–74, (1986).

    Google Scholar 

  6. N. P. Red’kin, “On Complete Fault Detection Tests for Logic Circuits,” in Mathematical Problems of Cybernetics, Vol. 2 (Nauka, Moscow, 1989), pp. 198–222.

    Google Scholar 

  7. D. S. Romanov, “On Synthesis of Circuits Admitting Complete Fault Detection Test Sets of Constant Length under Arbitrary Constant Faults at theOutputs of the Gates,” Diskretn.Mat. 25 (2), 104–120 (2013) [DiscreteMath. Appl. 23 (3–4), 343–362 (2013)].

    Article  Google Scholar 

  8. N. P. Red’kin, “On Circuits Admitting Short Tests,” VestnikMoskov.Univ. Ser. 1: Mat.Mekh.No. 2, 17–21 (1988).

    Google Scholar 

  9. Yu. V. Borodina, “Synthesis of Easily-Tested Circuits in the Case of Single-Type Constant Malfunctions at the Element Outputs,” VestnikMoskov. Univ. Ser. 15: Vychisl.Mat. Kibernet.No. 1, 40–44 (2008) [Moscow Univ. Comput. Math. Cybern. 32 (1), 42–46 (2008)].

    MATH  MathSciNet  Google Scholar 

  10. Yu. V. Borodina and P. A. Borodin, “Synthesis of Easily Testable Circuits over the Zhegalkin Basis in the Case of Constant Faults of Type 0 at Outputs of Elements,” Diskretn.Mat. 22 (3), 127–133 (2010) [Discrete Math. Appl. 20 (4), 441–449 (2010)].

    Article  MATH  Google Scholar 

  11. Yu. V. Borodina, “Lower Estimate of the Length of the Complete Test in the Basis x y,” Vestnik Moskov. Univ. Ser. 1: Mat.Mekh.No. 4, 49–51 (2015) [Moscow Univ.Math. Bull. 70 (4), 185–186 (2015)].

    MATH  MathSciNet  Google Scholar 

  12. S. M. Reddy, “Easily Testable Realization for Logic Functions,” IEEE Trans. Comput. 21 (1), 124–141 (1972).

    MathSciNet  Google Scholar 

  13. S. DasGupta, C. R. P. Hartmann, and L. D. Rudolph, “Dual-Mode Logic for Function-Independent Fault Testing,” IEEE Trans. Comput. 29 (11), 1025–1029 (1980).

    Article  MATH  MathSciNet  Google Scholar 

  14. V. Geetha, N. Devarajan, and P. N. Neelakantan, “Network Structure for Testability Improvement in Exclusive-OR Sum of Products Reed–Muller Canonical Circuits,” Int. J. Eng. Res. Gen. Sci. 3 (3), 368–378 (2015).

    Google Scholar 

  15. J. P. Hayes, “On Modifying Logic Networks to Improve Their Diagnosability,” IEEE Trans. Comput. 23 (1), 56–62 (1974).

    Article  MathSciNet  Google Scholar 

  16. T. Hirayama, G. Koda, Y. Nishitani, and K. Shimizu, “Easily TestableRealization Based on OR-AND-EXOR Expansion with Single-Rail Inputs,” IEICE Trans. Inform. Syst. E-82D (9), 1278–1286 (1999).

    Google Scholar 

  17. A. K. Jameil, “A New Single Stuck Fault Detection Algorithm for Digital Circuits,” Int. J. Eng. Res. Gen. Sci. 3 (1), 1050–1056 (2015).

    Google Scholar 

  18. P. N. Neelakantan and A. Ebenezer Jeyakumar, “Single Stuck-At Fault Diagnosing Circuit of Reed–Muller Canonical Exclusive-Or Sum of Product Boolean Expressions,” J. Comput. Sci. 2 (7), 595–599 (2006).

    Article  Google Scholar 

  19. N. P. Rahagude, “Integrated Enhancement of Testability and Diagnosability for Digitac Circuits,” Mast. Sci. Dissertation (VA Polytech. Inst. State Univ., Blacksburg, VA, 2010).

    Google Scholar 

  20. H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable Design of AND-EXOR Logic Networks with Universal Test Sets,” Comput. Electr. Eng.35 (5), 644–658 (2009).

    Google Scholar 

  21. K. K. Saluja and S.M. Reddy, “On Minimally Testable Logic Networks,” IEEE Trans. Comput. 23 (5), 552–554 (1974).

    Article  MATH  MathSciNet  Google Scholar 

  22. K. K. Saluja and S.M. Reddy, “Fault Detecting Test Sets for Reed–MullerCanonic Networks,” IEEE Trans. Comput. 24 (10), 995–998 (1975).

    Article  MathSciNet  Google Scholar 

  23. S. P. Singh and B. B. Sagar, “Stuck-At Fault Detection in Combinational Network Coefficients of the RMC with Fixed Polarity (Reed–MullerCoefficients),” Internat. J. Emerg. Trends Electr. Electron (IJETEE) 1 (3), 93–96 (2013).

    Google Scholar 

  24. K. A. Popkov, “Tests of Contact Closure for Contact Circuits,” Diskretn. Mat. 28 (1), 87–100 (2016) [DiscreteMath. Appl. 26 (5), 299–308 (2016)].

    Article  MATH  Google Scholar 

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Correspondence to K. A. Popkov.

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Russian Text © K.A. Popkov, 2019, published in Diskretnyi Analiz i Issledovanie Operatsii, 2019, Vol. 26, No. 1, pp. 89–113.

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Popkov, K.A. Short Complete Fault Detection Tests for Logic Networks with Fan-In Two. J. Appl. Ind. Math. 13, 118–131 (2019). https://doi.org/10.1134/S1990478919010137

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  • DOI: https://doi.org/10.1134/S1990478919010137

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