Abstract
The problem of construction of large-capacity comparators from programmable logic integrated circuits (PLICs) is discussed. A method for synthesizing large-capacity comparators with hierarchical pyramidal structures is proposed. This method is compared with two known (parallel and sequential) methods and two methods of the Altera MAX+PLUSII computer-aided design program package. The results of experimental studies have shown that, in the design of 64-bit comparators, the proposed method makes it possible to decrease the implementation cost on average by a factor of 1.09 to 1.54 and increase the processing speed on average by a factor of 3.79 to 7.17, depending on the family of PLICs.
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References
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MAX+PLUSII Programmable Logic Development System (Altera Corporation, 1991).
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Original Russian Text © V.V. Solov’ev, A.A. Posrednikova, 2009, published in Radiotekhnika i Elektronika, 2009, Vol. 54, No. 3, pp. 354–362.
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Solov’ev, V.V., Posrednikova, A.A. The hierarchical method of synthesis of large-capacity comparators with the use of programmable logic integrated circuits. J. Commun. Technol. Electron. 54, 338–346 (2009). https://doi.org/10.1134/S1064226909030139
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DOI: https://doi.org/10.1134/S1064226909030139