Abstract
Design of gallium arsenide heterojunction transistor integrated circuits for a limiting amplifier and synchronizer is considered. A novel circuitry of amplifying stages is proposed. Computer simulation is performed. Devices capable of 12.5-Gbps data transmission speed are investigated experimentally. Good agreement of experimental and simulation results is obtained.
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Original Russian Text © V.P. Timoshenkov, 2007, published in Radiotekhnika i Elektronika, 2007, Vol. 52, No. 7, pp. 888–896.
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Timoshenkov, V.P. Gallium arsenide heterojunction transistor integrated circuits for a limiting amplifier and synchronizer. J. Commun. Technol. Electron. 52, 826–834 (2007). https://doi.org/10.1134/S1064226907070169
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DOI: https://doi.org/10.1134/S1064226907070169