Degradation of the SrRuO₃/SrTiO₃ interface capacitance induced by mechanical stresses

Abstract

Trilayer epitaxial heterostructures in which a 700-nm-thick SrTiO₃ interlayer is integrated with two SrRuO₃ electrodes have been grown by laser ablation. In the top electrode, twenty contact pads (S ≈ 0.1 mm²) have been formed using photolithography and ion etching. The bottom SrRuO₃ electrode grown on a MgO(001) substrate is common for all film capacitors on the chip. As the temperature decreases in the range of 300-50 K, the capacitance C of the capacitors increases by a factor more than two due to an increase in the permittivity ɛ of the interlayer. At T = 4.2 K, as the bias voltage of ±2.5 V is applied to the oxide electrodes, the capacitance C decreases by ∼40%. In the temperature range of 100–300 K, the ratio ɛ₀/ɛ increases almost linearly with increasing temperature (ɛ₀ is the permittivity in vacuum). At T > 250 K, the dielectric loss tangent of the SrTiO₃ interlayer increases exponentially with increasing temperature and substantially depends on the bias voltage applied to the oxide electrodes.