Skip to main content
Log in

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

  • Published:
Russian Microelectronics Aims and scope Submit manuscript

Abstract

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical characteristics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.

REFERENCES

  1. Bravaix, A., Huard, V., Cacho, F., Federspiel, X., and Royl, D., Hot-carrier degradation in decananometer CMOS Nodes: From an energy-driven to a unified current degradation modeling by a multiple-carrier degradation process, Hot Carrier Degradation in Semiconductor Devices, Grasser, T., Ed., Wien: Springer, 2015, pp. 57–103. https://doi.org/10.1007/978-3-319-08994-2_3

    Book  Google Scholar 

  2. Moens, P. and van den Bosch, G., Characterization of total safe operating area of lateral DMOS transistors, IEEE Trans. Device Mater. Reliab., 2006, vol. 6, no. 3, pp. 349–357. https://doi.org/10.1109/tdmr.2006.882212

    Article  Google Scholar 

  3. Moens, P., Varghese, D., and Alam, M.A., Towards a universal model for hot carrier degradation in DMOS transistors, Proc. International Symposium on Power Semiconductor Devices and ICs, Barcelona, 2010, IEEE, 2010, pp. 61–64.

  4. Wang, W., Reddy, V., Krishnan, A.T., Vattikonda, R., Krishnan, S., and Cao, Y., Compact modeling and simulation of circuit reliability for 65 nm CMOS technology, IEEE Trans. Device Mater. Reliab., 2007, vol. 7, no. 4, pp. 509–517. https://doi.org/10.1109/TDMR.2007.910130

    Article  Google Scholar 

  5. Poli, S., Reggiani, S., Baccarani, G., Gnani, E., Gnudi, A., Denison, M., Pendharkar, S., and Wise, R., Hot-carrier stress induced degradation in Multi-STI-Finger LDMOS: An experimental and numerical insight, Solid-State Electron., 2011, vols. 65–66, pp. 57–63. https://doi.org/10.1016/j.sse.2011.06.007

    Article  Google Scholar 

  6. Bude, J. and Hess, K., Thresholds of impact ionization in semiconductors, J. Appl. Phys., 1992, vol. 72, no. 8, pp. 3554–3561. https://doi.org/10.1063/1.351434

    Article  Google Scholar 

  7. Hu, Ch., Tam, S.C., Hsu, F.-Ch., Ko, P.-K., Chan, T., and Terrill, K.W., Hot-electron-induced MOSFET degradation-Model, monitor, and improvement, IEEE J. Solid-State Circuits, 1985, vol. 32, no. 1, pp. 295–305.

    Google Scholar 

  8. Ancona, M.G., Saks, N.S., and McCarthy, D., Lateral distribution of hot-carrier-induced interface traps in MOSFETs, IEEE Trans. Electron Devices, 1988, vol. 35, no. 12, pp. 2221–2228. https://doi.org/10.1109/16.8796

    Article  Google Scholar 

  9. Di Maria, D.J. and Stasiak, J.W., Trap creation in silicon dioxide produced by hot electrons, J. Appl. Phys., 1989, vol. 65, no. 6, pp. 2342–2357. https://doi.org/10.1063/1.342824

    Article  Google Scholar 

  10. Yassine, A.M., Nariman, H.E., McBride, M., Uzer, M., and Olasupo, K.R., Time dependent breakdown of ultrathin gate oxide, IEEE Trans. Electron Devices, 2000, vol. 47, no. 7, pp. 1416–1420. https://doi.org/10.1109/16.848285

    Article  Google Scholar 

  11. Wang, L., Wang, J., Gao, C., Hu, J., Li, P.Z.X., Li, W., and Yang, S.H.Y., Physical description of quasi-saturation and impact-ionization effects in high-voltage drain-extended MOSFETs, IEEE Trans. Electron Devices, 2009, vol. 56, no. 3, pp. 492–498. https://doi.org/10.1109/ted.2008.2011575

    Article  Google Scholar 

  12. Varghese, D., Kufluoglu, H., Reddy, V., Shichijo, H., Mosher, D., Krishnan, S., and Alam, M.A., OFF-state degradation in drain-extended NMOS transistors: Interface damage and correlation to dielectric breakdown, IEEE Trans. Electron Devices, 2007, vol. 54, no. 10, pp. 2669–2678. https://doi.org/10.1109/ted.2007.904587

    Article  Google Scholar 

  13. Varghese, D., Moens, P., and Alam, M.A., ON-state hot carrier degradation in drain-extended NMOS transistors, IEEE Trans. Electron Devices, 2010, vol. 57, no. 10, pp. 2704–2710. https://doi.org/10.1109/ted.2010.2059632

    Article  Google Scholar 

  14. Hong, S.-M., Pham, A.-T., and Jungemann, C., Deterministic Solvers for the Boltzmann Transport Equation, Computational Microelectronics, Vienna: Springer, 2011. https://doi.org/10.1007/978-3-7091-0778-2

  15. Cheng, S.-W., Dey, T.K., and Shewchuk, J.R., Delaunay Mesh Generation, New York: Chapman and Hall/CRC, 2013. https://doi.org/10.1201/b12987

    Book  MATH  Google Scholar 

  16. Rudolf, F., Weinbub, J., Rupp, K., and Selberherr, S., The meshing framework ViennaMesh for finite element applications, J. Comput. Appl. Math., 2014, vol. 167, pp. 166–177. https://doi.org/10.1016/j.cam.2014.02.005

    Article  MathSciNet  MATH  Google Scholar 

  17. Penzin, O., Haggag, A., McMahon, W., Lyumkis, E., and Hess, K., MOSFET degradation kinetics and its simulation, IEEE Trans. Electron Devices, 2003, vol. 50, no. 6, pp. 1445–1450. https://doi.org/10.1109/ted.2003.813333

    Article  Google Scholar 

  18. Reggiani, S., Barone, G., Gnani, E., Gnudi, A., Baccarani, G., Poli, S., Wise, R., Chuang, M.-Ye., Tian, W., Pendharkar, S., and Denison, M., Characterization and modeling of electrical stress degradation in STI-based integrated power devices, Solid-State Electron., 2014, vol. 102, no. 12, pp. 25–41. https://doi.org/10.1016/j.sse.2014.06.008

    Article  Google Scholar 

  19. Reggiani, S., Barone, G., Gnani, E., Gnudi, A., Baccarani, G., Poli, S., Wise, R., Chuang, M.-Ye., Tian, W., Pendharkar, S., and Denison, M., Characterization and modeling of high-voltage LDMOS transistors, Hot Carrier Degradation in Semiconductor Devices, Grasser, T., Ed., Heidelberg: Springer, 2015, pp. 309–339. https://doi.org/10.1007/978-3-319-08994-2_11

    Book  Google Scholar 

  20. Rumyantsev, S.V., Novoselov, A.S., and Masal’skii, N.V., Investigating the electrothermal characteristics of partially depleted submicron SOI CMOS transistors in an extended temperature range, Russ. Microelectron., 2020, vol. 49, no. 1, pp. 30–36. https://doi.org/10.1134/s1063739720010102

    Article  Google Scholar 

  21. Guerin, C., Huard, V., and Bravaix, A., General framework about defect creation at the Si/SiO2 interface, J. Appl. Phys., 2009, vol. 105, no. 11, p. 114513. https://doi.org/10.1063/1.3133096

    Article  Google Scholar 

  22. Stesmans, A., Passivation of P b0 and P b1 interface defects in thermal (100) Si/SiO2 with molecular hydrogen, Appl. Phys. Lett., 1996, vol. 68, no. 15, pp. 2076–2078. https://doi.org/10.1063/1.116308

    Article  Google Scholar 

  23. Sharma, P., Tyaginov, S., Wimmer, Ya., Rudolf, F., Rupp, K., Bina, M., Enichlmair, H., Park, J.-M., Minixhofer, R., Ceric, H., and Grasser, T., Modeling of hot-carrier degradation in nLDMOS devices: Different approaches to the solution of the Boltzmann transport equation, IEEE Trans. Electron Devices, 2015, vol. 62, no. 6, pp. 1811–1818. https://doi.org/10.1109/ted.2015.2421282

    Article  Google Scholar 

  24. De Jong, M.J., Salm, C., and Schmitz, J., Towards understanding recovery of hot-carrier induced degradation, Microelectron. Reliab., 2018, vols. 88–90, pp. 147–151. https://doi.org/10.1016/j.microrel.2018.07.057

    Article  Google Scholar 

  25. Yu, Z., Zhang, Z., Sun, Z., Wang, R., and Huang, R., On the trap locations in bulk FinFETs after hot carrier degradation (HCD), IEEE Trans. Electron Devices, 2020, vol. 67, no. 7, pp. 3005–3009. https://doi.org/10.1109/ted.2020.2994171

    Article  Google Scholar 

Download references

Funding

This study was supported as part of a state task of the Scientific Research Institute for System Analysis, Russian Academy of Sciences on carrying out fundamental scientific research (47 GP) on the research topic “Fundamental and applied research in the field of lithographic thresholds of semiconductor technologies and physicochemical processes of etching 3D nanometer dielectric structures for the development of critical technologies for the production of electronic components. Research and construction of models and designs of microelectronic elements in an extended temperature range (from –60 to +300°С) (FNEF-2022-0006).”

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to A. S. Novoselov.

Ethics declarations

The authors declare that they have no conflicts of interest.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Novoselov, A.S., Masalskii, N.V. Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region. Russ Microelectron 52, 411–418 (2023). https://doi.org/10.1134/S1063739723700580

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S1063739723700580

Keywords:

Navigation