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Failure-Tolerant Synchronous and Self-Timed Circuits Comparison

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Abstract

The article considers the problem of developing synchronous and self-timed (ST) digital circuits tolerant to soft errors. Synchronous circuits traditionally use the “2-of-3” voting principle to ensure a single failure, resulting in three times the hardware costs. Due to dual-rail signal coding and two-phase control in ST circuits, duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits’ failure tolerance.

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Funding

This work was supported by the Russian Science Foundation, project no. 22-19-00237.

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Authors and Affiliations

  1. Institute of Informatics Problems, Federal Research Center “Computer Science and Control” of Russian Academy of Sciences, 119333, Moscow, Russia

    A. A. Zatsarinny, Yu. A. Stepchenkov, Yu. G. Diachenko & Yu. V. Rogdestvenski

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  1. A. A. Zatsarinny
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  2. Yu. A. Stepchenkov
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  3. Yu. G. Diachenko
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  4. Yu. V. Rogdestvenski
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Correspondence to Yu. A. Stepchenkov.

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Zatsarinny, A.A., Stepchenkov, Y.A., Diachenko, Y.G. et al. Failure-Tolerant Synchronous and Self-Timed Circuits Comparison. Russ Microelectron 51, 630–632 (2022). https://doi.org/10.1134/S1063739722080091

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  • DOI: https://doi.org/10.1134/S1063739722080091

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