Abstract
One of the main advantages of FPGA design flow is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resources graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. The sets of test digital circuits ISCAS’85, ISCAS’89, LGSynth’89 and several custom industrial projects were used for computational experiments. The impact of the proposed algorithmic improvements was analyzed using four FPGA architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA architecture, with no significant negative effect on the timing characteristics of the designed circuits.
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1134%2FS1063739722070125/MediaObjects/11180_2022_7343_Fig1_HTML.png)
Similar content being viewed by others
REFERENCES
McMurchie, L. and Ebeling, C., PathFinder: A negotiation-based performance-driven router for FPGAs, in FPGA’95: Proceedings of the 1995 ACM 3rd International Symposium on Field-Programmable Gate Arrays, New York: ACM, 1995, pp. 111–117. https://doi.org/10.1145/201310.201328
Zhou, Y., Vercruyce, D., and Stroobandt, D., Accelerating FPGA routing through algorithmic enhancements and connection-aware parallelization, ACM Trans. Reconfig. Technol. Syst., 2020, vol. 13, no. 4, p. 18. https://doi.org/10.1145/3406959
Murray, K.E., Petelin, O., Zhong, Sh., et al., VTR 8: High-performance CAD and customizable FPGA architecture modelling, ACM Trans. Reconfig. Technol. Syst., 2020, vol. 13, no. 2, p. 9. https://doi.org/10.1145/3388617
Pan, M., Xu, Y., Zhang, Y., and Chu, Ch., Fastroute: An efficient and high-quality global router, VLSI Design, 2012, vol. 2012, p. 608362. https://doi.org/10.1155/2012/608362
He, J., Burtscher, M., Manohar, R., and Pingali, K., SPRoute: A scalable parallel negotiation-based global router, in Proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2019), Westminster, CO: IEEE, 2019, pp. 1–8. https://doi.org/10.1109/ICCAD45719.2019.8942105
Vercruyce, D., Vansteenkiste, E., and Stroobandt, D., Croute: A fast high-quality timing-driven connection-based FPGA router, in Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), San Diego, CA: IEEE, 2019, pp. 53–60. https://doi.org/10.1109/FCCM.2019.00017
Murray, K.E., Zhong, S., and Betz, V., AIR: A fast but lazy timing-driven FPGA router, in Proceedings of the 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing: IEEE, 2020, pp. 338–344. https://doi.org/10.1109/ASP-DAC47756.2020.9045175
Hoo, C.H. and Kumar, A., ParaDRo: A parallel deterministic router based on spatial partitioning and scheduling, in FPGA’18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, New York: ACM, 2018, pp. 67–76. https://doi.org/10.1145/3174243.3174246
Fraisse, H., Incremental routing for circuit designs using a SAT router, U.S. Patent no. 10445456, 2019.
Alawieh, M.B., Li, W., Lin, Y., et al., High-definition routing congestion prediction for large-scale FPGAs, in Proceedings of the 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing: IEEE, 2020, pp. 26–31. https://doi.org/10.1109/ASP-DAC47756.2020.9045178
Li, W., Dehkordi, M.E., Yang, S., and Pan, D.Z., Simultaneous placement and clock tree construction for modern FPGAs, in FPGA’19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, New York: ACM, 2019, pp. 132–141. https://doi.org/10.1145/3289602.3293897
Kannan, P. and Bhatia, D., Tightly integrated placement and routing for FPGAs, in FPL 2001: Field-Programmable Logic and Applications, Berlin: Springer, 2001, pp. 233–242. https://doi.org/10.1007/3-540-44687-7_25
Liu, W.-H., Kao, W.-C., Li, Y.-L., and Chao, K.-Y., Multi-threaded collision-aware global routing with bounded-length maze routing, in Proceedings of the Design Automation Conference, Anaheim, CA: IEEE, 2010, pp. 200–205.
Pan, M. and Chu, C., IPR: An integrated placement and routing algorithm, in Proceedings of the 2007 44th ACM/IEEE Design Automation Conference, San Diego, CA: IEEE, 2007, pp. 59–62.
Zmeev, D.N., Levchenko, N.N., Okunev, A.S., and Stempkovskii, A.L., Impact of features of the computing model and architecture on the parallel dataflow computing system reliability, Probl. Razrab. Persp. Mikro- Nanoelektron. Sist., 2020, no. 1, pp. 64–69. https://doi.org/10.31114/2078-7707-2020-1-64-69
Brglez, F. and Fujiwara, H., A neutral netlist of 10 combinational circuits and a targeted translator in Fortran, in Proceedings of the Special Session on Recent Algorithms for Gate-Level ATPG with Fault Simulation and Their Performance Assessment, 1985, IEEE International Symposium on Circuits and Systems, Kyoto: IEEE, 1985, pp. 663–698.
Brglez, F., Bryan, D., and Kozminski, K., Combinational profiles of sequential benchmark circuits, in Proceedings of the IEEE International Symposium on Circuits and Systems, Portland, OR: IEEE, 1989, vol. 3, pp. 1929–1934. https://doi.org/10.1109/ISCAS.1989.100747
Yang, S., Logic synthesis and optimization benchmarks, Technical Report, in Proceedings of the 1989 MCNC International Workshop on Logic Synthesis, NC: MCNC, 1989, p. 14.
Zheleznikov, D.A., Zapletina, M.A., and Khvatov, V.M., The rip-up and reroute technique research for physical synthesis in the basis of reconfigurable socs, Probl. Razrab. Persp. Mikro- Nanoelektron. Sist., 2018, no. 1, pp. 188–192. https://doi.org/10.31114/2078-7707-2018-1-188-192
Gavrilov, S.V., Zheleznikov, D.A., Zapletina, M.A., Khvatov, V.M., Chochaev, R.Zh., and Enns, V.I., Layout synthesis design flow for special-purpose reconfigurable systems-on-a-chip, Russ. Microelectron., 2019, vol. 48, no. 3, pp. 176–186. https://doi.org/10.1134/S1063739719030053
PATsIS 5400TR094. https://dcsoyuz.ru/search/art/1605. Accessed April 6, 2021.
ProASIC3 series, Microchip Technology Inc. http:// www.microsemi.com/product-directory/fpgas/1690-proasic3. Accessed April 6, 2021.
Intel MAX II Device Handbook (Altera Corp., 2009). http://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii5v1.pdf. Accessed April 6, 2021.
Funding
This work was supported by the Russian Foundation for Basic Research (project no. 20-37-90046).
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
The authors declare that they have no conflicts of interest.
Rights and permissions
About this article
Cite this article
Zapletina, M.A., Gavrilov, S.V. Pathfinder Algorithm Modification for FPGA Routing Stage. Russ Microelectron 51, 573–578 (2022). https://doi.org/10.1134/S1063739722070125
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1134/S1063739722070125