Abstract
For the development of the market of modern microelectronics, methods are required that allow continuously increasing the productivity and energy efficiency of semiconductor products and, at the same time, reducing the required minimum area of the crystal while maintaining its functionality. Therefore, the integration of nonvolatile elements (memristors) and CMOS technologies, as well as the creation of methods for synthesizing digital circuits with smmristor functional units—memristor logic (MeMOS logic)—are urgent problems. The paper proposes a block method for the synthesis of hybrid MeMOS circuits, using minterm maps, which makes it possible to simultaneously synthesize a MeMOS circuit and optimize it. Examples of the synthesis of combinational (Exclusive OR) and sequential (RS-trigger) schemes. The existing and new variants of solutions to problems of the synthesis of combinational and sequential integrated circuits with memristors are considered. It is shown that the average power dissipated RS-trigger is 7.7 μW for the standard logic and 2.2 μW for the memristor logic. The power consumption of the XOR circuit is 13 μW for the standard logic and 9.2 μW for the memristor logic.
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REFERENCES
International Technology Roadmap for Semiconductors, Executive Summary, ITRS, 2011. http://www. itrs. net/Links/2011ITRS/2011Chapters/2011ExecSum.pdf. Accessed April 10, 2020.
Cho, K., Lee, S.-J., and Eshraghian, K., Memristor-CMOS logic and digital computational components, Microelectron. J., 2015, vol. 46, no. 3, pp. 214–220.
Kulakova, A.A. and Luk’yanenko, E.B., Circuitry of D‑flip-flops—basic elements of the sequential VLSI, Nano- Mikrosist. Tekh., 2019, vol. 21, no. 7, pp. 422–429.
Sharma, G. and Bhargava, L., CMOS-memristor inverter circuit design and analysis using Cadence Virtuoso, in Proceedings of the 2016 International Conference on Recent Advances and Innovations in Engineering, 2016, pp. 1–5.
Sasi, A. and Amirsoleimani, A., Hybrid memristor-CMOS based linear feedback shift register design, in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, Batumi, 2017, pp. 62–65.
Lalchhandama, F. and Gopal, B., An improved approach for the synthesis of boolean functions using memristor based IMPLY and INVERSE-IMPLY gates, in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, 2016, pp. 319–324.
Kvatinsky, S., Belousov, D., Liman, S., et al., MAGIC-memristor aided LoGIC, IEEE Trans. Circuits Syst. II: Express Briefs, 2014, vol. 61, no. 11, pp. 895–899.
Kvatinsky, S., Wald, N., Satat, G., et al., Memristor-based material implication (imply) logic: design principles and methodologies, IEEE Trans. Very Large Scale Integr., 2013, vol. 22, no. 10, pp. 2054–2066. https://doi.org/10.1109/TVLSI.2013.2282132
Kvatinsky, S., Wald, N., Satat G., et al., MRL—Memristor Ratioed Logic, in Proceedings of the International Cellular Nanoscale Networks and Their Applications, August, 2012, pp. 1–6.
Guckert, L. and Swartzlander, E.E., MAD gates— memristor logic design using driver circuitry, IEEE Trans. Circuits Syst. II: Express Briefs, 2017, vol. 64, no. 2, pp. 171–175.
Teimoory, M., Amirsoleimani, A., Ahmadi, A., and Ahmadi, M., A hybrid memristor-CMOS multiplier design based on memristive universal logic gates, in Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, Boston, MA, 2017, pp. 1422–1425.
Chua, L.O., Memristor: the missing circuit element, IEEE Trans. Circuit Theory, 1971, no. 18, pp. 507–519.
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Kulakova, A.A., Lukyanenko, E.B. Memristor Logic in Digital Circuitry. Russ Microelectron 50, 523–527 (2021). https://doi.org/10.1134/S1063739721070088
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DOI: https://doi.org/10.1134/S1063739721070088