The Element of Matching on an STG DICE Cell for an Upset Tolerant Content Addressable Memory
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The TCAD simulation of charge collection from tracks of single nuclear particles directed along the normal to the logic matching element on STG DICE cells demonstrates their unique upset tolerance. The tracks used for simulation are directed normal to the microchip surface with the linear energy transfer (LET) ranging from 10 to 60 MeV cm2/mg. We investigate a 65-nm bulk CMOS logic matching element for use in content addressable memory and translation lookaside buffers. It is a matching element on an STG DICE cell with an exclusive OR logic element on two tristate inverters. The linear energy transfers in the range of 30–60 MeV cm2/mg on the tracks normal to the chip surface do not cause single event upsets in the STG DICE cell for LET = 60 MeV cm2/mg. In the output combinational logic of the matching element, short (up to 0.6 ns) noise voltage pulses for a LET ranging from 20 to 60 MeV cm2/mg can be found.
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