Skip to main content
SpringerLink
Log in

Synthesis of Test Sequences with a Given Switching Activity

  • OPTIMIZATION, SYSTEM ANALYSIS, OPERATIONS RESEARCH
  • Published:
Automation and Remote Control Aims and scope Submit manuscript

Abstract

The relevance of using test sequences with a given switching activity is discussed. As a mathematical model for generating the tests, a modification of the Antonov–Saleev method for generating Sobol sequences is used. It is based on the use of maximum-rank generating matrices the form of which determines the main properties of the sequences. It is shown that the construction of a generating matrix is reduced to the problem of partitioning an integer, and an algorithm for splitting into summands of a given form is proposed. Procedures for modifying the partition of an integer into summands and for modifying the value of switching activity are introduced. Three problems are stated for the synthesis of generators of test sequences with a given switching activity. Examples of using the proposed methods and experimental results are considered.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.

Similar content being viewed by others

REFERENCES

  1. Jha, N.K. and Gupta, S., Testing of Digital Systems, Cambridge, UK: Cambridge Univ. Press, 2003.

    Book  Google Scholar 

  2. Yarmolik, V.N., Kontrol’ i diagnostika vychislitel’nykh sistem (Control and Diagnostics of Computer Systems), Minsk: Bestprint, 2019.

    Google Scholar 

  3. Bushnell, M.L.AgrawalV.D., Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, New York: Kluwer, 2000.

    Google Scholar 

  4. Sharma, A.K., Semiconductor Memories: Technology, Testing, and Reliability, London: John Wiley & Sons, 2002.

    Book  Google Scholar 

  5. Wang, S. and Gupta, S.K., An automatic test pattern generator for minimizing switching activity during scan testing activity, IEEE Trans. Comp. Aided Des. Int. Cirs. Syst., 2002, vol. 21, no. 8, pp. 954–968.

    Article  Google Scholar 

  6. Goor, A.J., Kukner, H., and Hamdioui, S., Optimizing memory BIST Address Generator implementations, Proc. 6th Int. Conf. Des. & Tech. Integr. Syst. Nanoscale Era (DTIS) (2011), pp. 572–576.

  7. Pedram, M., Power minimization in IC design: principles and applications, ACM Trans. Des. Autom. Electr. Syst., 1996, vol. 1, pp. 3–56.

    Article  Google Scholar 

  8. Murashko, I.A. and Yarmolik, V.N., Vstroennoe samotestirovanie. Metody minimizatsii energopotrebleniya (Built-In Self-Testing. Energy Minimization Methods), Minsk: Bestprint, 2008.

    Google Scholar 

  9. Girard, P., Guiller, L., Landrault, S., et al., A test vector ordering technique for switching activity reduction during test operation, Proc. Ninth Great Lakes Symp. VLSI (1999), pp. 24–27.

  10. Bellaouar, A. and Elmasry, M., Low-Power Digital VLSI Design Circuits and Systems, New York: Springer, 1996.

    Google Scholar 

  11. Huang, R., Sun, W., Xu, Y., et al., A survey on adaptive random testing, IEEE Trans. Soft. Eng., 2015, vol. 14, no. 8, pp. 1–36.

    Google Scholar 

  12. Mrozek, I. and Yarmolik, V.N., Iterative antirandom testing, J. Electr. Test: Theory Appl., 2012, vol. 9, no. 3, pp. 251–266.

    MATH  Google Scholar 

  13. Chen, T.Y., Kuo, F.C., Merkel, R.G., et al., Adaptive Random Testing: the ART of test case diversity, J. Syst. Software, 2010, vol. 83, no. 1, pp. 60–66.

    Article  Google Scholar 

  14. Mrozek, I. and Yarmolik, V.N., Antirandom test vectors for BIST in Hardware. Software systems, in Fundamenta Informaticae, 2012, no. 119, pp. 1–23.

  15. Yarmolik, S.V. and Yarmolik, V.N., Controlled random tests, Autom. Remote Control, 2012, vol. 73, no. 10, pp. 1704–1714.

    Article  MathSciNet  Google Scholar 

  16. Du, X., Mukherjee, N., Cheng, W.T., et al., Full-speed field-programmable memory BIST architecture, Proc. IEEE Int. Test Conf. (2005), pp. 1173–1182.

  17. Aswin, A.M. and Ganesh, S.S., Implementation and validation of memory built in self-test (MBIST)—survey, Int. J. Mech. Eng. Tech., 2019, vol. 10, no. 3, pp. 153–160.

    Google Scholar 

  18. Yarmolik, V.N. and Yarmolik, S.V., The repeated nondestructive march tests with variable address sequences, Autom. Remote Control, 2007, vol. 68, no. 4, pp. 126–137.

    Article  MathSciNet  Google Scholar 

  19. Yarmolik, V.N. and Shevchenko, N.A., Formation of address sequences with a given switching activity, Informatika, 2020, vol. 17, no. 1, pp. 7–23.

    Google Scholar 

  20. Sobol, I.M., Tochki, ravnomerno zapolnyayushchie mnogomernyi kub (Points Uniformly Filling a Multidimensional Cube), Moscow: Znanie, 1985.

    MATH  Google Scholar 

  21. Antonov, I.A. and Saleev, V.M., An economic method of computing LP \( _\tau \)-sequences, USSR Comput. Math. Math. Phys., 1979, vol. 19, no. 1, pp. 252–256.

    Article  Google Scholar 

  22. Yarmolik, S.V. and Yarmolik, V.N., Quasirandom testing of computing systems, Informatika, 2013, no. 3(39), pp. 65–81.

  23. Savage, C., A survey of combinatorial Gray code, SIAM Rev., 1997, vol. 39, no. 4, pp. 605–629.

    Article  MathSciNet  Google Scholar 

  24. Pomeranz, I., An adjacent switching activity metric under functional broadside tests, IEEE Trans. Comput., 2013, vol. 62, no. 4, pp. 404–410.

    Article  MathSciNet  Google Scholar 

  25. Knuth, D.E., The Art of Computer Programming. Vol. 4A. Part 1. Combinatorial Algorithms, Upper Saddle River, NJ: Addison-Wesley, 2011. Translated under the title: Iskusstvo programmirovaniya. T. 4A. Kombinatornye algoritmy. Ch. 1 , Moscow: Williams, 2013.

    MATH  Google Scholar 

  26. McKay, J.K.S., Algorithm 371: Partitions in natural order [A1], Commun. ACM, 1970, vol. 13, no. 1, p. 52.

    Article  Google Scholar 

  27. Stojmenović, I. and Zoghbi, A., Fast algorithms for generating integer partitions, Int. J. Comput. Math., 1998, vol. 70, no. 2, pp. 319–332.

  28. Ferreira, P., Jesus, B., Armando, J.V., and Pinho, J., The rank of random binary matrices and distributed storage applications, IEEE Commun. Lett., 2013, vol. 17, no. 1, pp. 151–154.

    Article  Google Scholar 

  29. Shauchenka, M., Address sequence generator for memory BIST, SSRG–IJCSE, 2019, vol. 6, no. 11, pp. 22–26.

    Article  Google Scholar 

  30. Shauchenka, M., Address sequence generator for memory BIST investigation, Int. Sci. J. Sci. Tech. Union Mech. Eng.—Math. Model., 2020, vol. 4, no. 1, pp. 7–8.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Belarusian State University of Informatics and Radioelectronics, Minsk, 220013, Belarus

    V. N. Yarmolik

  2. Lichtenbergschule Gymnasium, Darmstadt, 64285, Germany

    N. A. Shevchenko

Authors
  1. V. N. Yarmolik
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. N. A. Shevchenko
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to V. N. Yarmolik or N. A. Shevchenko.

Additional information

Translated by V. Potapchouck

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yarmolik, V.N., Shevchenko, N.A. Synthesis of Test Sequences with a Given Switching Activity. Autom Remote Control 83, 291–302 (2022). https://doi.org/10.1134/S0005117922020114

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S0005117922020114

Keywords

Search

Navigation