Skip to main content
SpringerLink
Log in

Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems

  • CONTROL IN TECHNICAL SYSTEMS
  • Published:
Automation and Remote Control Aims and scope Submit manuscript

Abstract

The paper deals with a comparative analysis of the efficiency of using synchronous and self-timed (ST) methodologies in the design of failure-tolerant computing and control systems based on complementary metal–oxide–semiconductor (CMOS) technology. The issues of failure tolerance of technical control means are considered in detail using examples of digital circuits of various types. A significant increase (by a factor of 1.2–1.8) in the time of failure-free operation of ST circuits in comparison with synchronous counterparts is confirmed. The most significant features of ST circuitry, which provide an increase in the failure tolerance of ST systems, are highlighted. Circuitry methods are proposed for increasing the failure tolerance of ST control systems, increasing the time of failure-free operation of combinational ST circuits up to 4.0 times and sequential ST circuits up to 7.1 times.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.

Similar content being viewed by others

REFERENCES

  1. Viktorova, V.C., Lubkov, N.V., and Stepanyants, A.S., Analiz nadezhnosti otkazoustoichivykh upravlyayushchikh vychislitel’nykh sistem (Reliability Analysis of Failure-Tolerant Control Computing Systems), Moscow: Inst. Probl. Upr. Ross. Akad. Nauk, 2016. https://www.ipu.ru/sites/default/files/card_file/VLS.pdf .

    Google Scholar 

  2. Kishinevsky, M., Kondratyev, A., Taubin, A., and Varshavsky, V., Concurrent Hardware: the Theory and Practice of Self-Timed Design, New York: John Wiley & Sons, 1994.

    MATH  Google Scholar 

  3. Zakharov, V., Stepchenkov, Y., Diachenko, Y., and Rogdestvenski, Y., Self-timed circuitry retrospective, Int. Conf. Eng. Technol. Comput. Sci. (EnT) (Moscow, 2020), pp. 58–64.

  4. Tabassam, Z., Naqvi, S.R., Akram, T., Alhussein, M., Aurangzeb, K., and Haider, S.A., Towards designing asynchronous microprocessors: from specification to tape-out, IEEE Access, 2019, vol. 7, no. 5, pp. 33978–34003. https://doi.org/10.1109/ACCESS.2019.2903126

    Article  Google Scholar 

  5. Smith, S.C. and Jia, Di., Designing asynchronous circuits using NULL Convention Logic (NCL), Synthesis Lect. Digital Circuits Syst., 2009, vol. 4, no. 1, pp. 61–73. https://doi.org/10.2200/S00202ED1V01Y200907DCS023

    Article  Google Scholar 

  6. Stepchenkov, Yu.A., Denisov, A.N., Diachenko, Yu.G., Grinfel’d, F.I., Filimonenko, O.P., Morozov, N.V., Stepchenkov, D.Yu., and Plekhanov, L.P., Biblioteka funktsional’nykh yacheek dlya proektirovaniya samosinkhronnykh poluzakaznykh BMK mikroskhem serii 5503/5507 (Library of Functional Cells for Designing Self-Timed Semicustom Array Chip Microcircuits of the 5503/5507 Series), Moscow: Tekhnosfera, 2017. http://www.technosphera.ru/lib/book/497 .

    Google Scholar 

  7. Lodhi, F.K., Hasan, S., Hasan, O., and Awwad, F., Low power soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline, IEEE Comput. Soc. Annu. Symp. VLSI (Tampa, Florida, USA, 2014), pp. 601–606.

  8. Iturbe, X., Venu, B., Ozer, E., and Das, S., A Triple Core Lock-step (TCLS) ARM Cortex-R5 processor for safety-critical and ultra-reliable applications, 46th Annu. IEEE/IFIP Int. Conf. Dependable Syst. Networks Workshop (DSN-W) (2016), pp. 246–249.

  9. Gkiokas, C. and Schoeberl, M.A., Fault-tolerant time-predictable processor, IEEE Nordic Circuits Syst. Conf. (NORCAS): NORCHIP Int. Sympos. System-on-Chip (SoC) (2019), pp. 1–6.

  10. Mavis, D. and Eaton, P., SEU and SET modeling and mitigation in deep submicron technologies, IEEE Int. Reliability Phys. Sympos. (Phoenix, Arizona, USA, April 15–19, 2007), pp. 293–305.

  11. Rogdestvenski, Yu.V., Stepchenkov, Yu.A., Diachenko, Yu.G., Morozov, N.V., Stepchenkov, D.Yu., and Diachenko, D.Yu., Method for increasing the speed of a self-timed multiplier, in Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem. Vyp. 1 (Problems of Developing Promising Micro- and Nanoelectronic Systems. Issue 1), Moscow: Inst. Probl. Proekt. Mikroelektron., 2020, pp. 82–88. https://doi.org/10.31114/2078-7707-2020-1-82-88

    Google Scholar 

  12. Sokolov, I.A., Stepchenkov, Yu.A., Diachenko, Yu.G., and Rogdestvenski, Yu.V., Improving the failure tolerance of self-timed circuits, Inf. Primen., 2020, vol. 14, no. 4, pp. 63–68.

    Google Scholar 

  13. Stepchenkov, Y.A., Kamenskih, A.N., Diachenko, Y.G., Rogdestvenski, Y.V., and Diachenko, D.Y., Improvement of the natural self-timed circuit tolerance to short-term soft errors, Adv. Sci. Technol. Eng. Syst. J., 2020, vol. 5, no. 2, pp. 44–56. https://doi.org/10.25046/aj050206.

    Article  Google Scholar 

  14. Emeliyanov, V.V., Vatuev, A.S., and Useinov, R.G., Impact of heavy ion energy on charge yield in silicon dioxide, IEEE Trans. Nucl. Sci., 2018, vol. 65, no. 8, pp. 1596–1502. https://doi.org/10.1109/TNS.2018.2813669

    Article  Google Scholar 

  15. Dubrova, E., Fault-Tolerant Design, Berlin: Springer, 2013. https://doi.org/10.1007/978-1-4614-2113-9

    Book  Google Scholar 

  16. Sokolov, I.A., Zakharov, V.N., Stepchenkov, Yu.A., and Diachenko, Yu.G., RF Patent no. 2725778, Self-timed failsafe storage register bit device, Byull. Izobret., 2020, no. 19.

  17. Sokolov, I.A., Zakharov, V.N., Stepchenkov, Yu.A., and Diachenko, Yu.G., RF Patent no. 2733263, Self-timed failsafe storage register bit device, Byull. Izobret., 2020, no. 28.

  18. Sokolov, I., Stepchenkov, Y., Diachenko, Y., Rogdestvenski, Y., and Diachenko, D., Increasing self-timed circuit soft error tolerance, IEEE EastWest Design & Test Sympos. (EWDTS) (Varna, Bulgaria, 2020), pp. 450–454.

  19. Makino, H., Nakase, Y., Suzuki, H., Morinaka, H., Shinohara, H., and Mashiko, K., An 8.8 ns 54x54 bit multiplier with high speed redundant binary architecture, IEEE J. Solid-State Circuits, 1996, vol. 31, no. 6, pp. 773–783. https://doi.org/10.1109/4.509863

    Article  Google Scholar 

  20. Stepchenkov, Y.A., Diachenko, Y.G., Rogdestvenski, Y.V., Diachenko, D.Yu., and Shikunov, Yu.I., Self-timed multiply-add-subtract unit alternates, IEEE Conf. Russ. Young Researchers Electr. Electron. Eng. (EIConRus) (2020), pp. 1864–1868.

Download references

Funding

The study was financially supported by the Ministry of Science and Higher Education of the Russian Federation, project no. 075-15-2020-799.

Author information

Authors and Affiliations

  1. Federal Research Center “Computer Science and Control,” Russian Academy of Sciences, Moscow, 119333, Russia

    I. A. Sokolov, Yu. A. Stepchenkov, Yu. V. Rogdestvenski & Yu. G. Diachenko

Authors
  1. I. A. Sokolov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yu. A. Stepchenkov
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yu. V. Rogdestvenski
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Yu. G. Diachenko
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to I. A. Sokolov, Yu. A. Stepchenkov, Yu. V. Rogdestvenski or Yu. G. Diachenko.

Additional information

Translated by V. Potapchouck

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sokolov, I.A., Stepchenkov, Y.A., Rogdestvenski, Y.V. et al. Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems. Autom Remote Control 83, 264–272 (2022). https://doi.org/10.1134/S0005117922020084

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S0005117922020084

Keywords

Search

Navigation