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Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems

Abstract

The paper deals with a comparative analysis of the efficiency of using synchronous and self-timed (ST) methodologies in the design of failure-tolerant computing and control systems based on complementary metal–oxide–semiconductor (CMOS) technology. The issues of failure tolerance of technical control means are considered in detail using examples of digital circuits of various types. A significant increase (by a factor of 1.2–1.8) in the time of failure-free operation of ST circuits in comparison with synchronous counterparts is confirmed. The most significant features of ST circuitry, which provide an increase in the failure tolerance of ST systems, are highlighted. Circuitry methods are proposed for increasing the failure tolerance of ST control systems, increasing the time of failure-free operation of combinational ST circuits up to 4.0 times and sequential ST circuits up to 7.1 times.

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Funding

The study was financially supported by the Ministry of Science and Higher Education of the Russian Federation, project no. 075-15-2020-799.

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Correspondence to I. A. Sokolov, Yu. A. Stepchenkov, Yu. V. Rogdestvenski or Yu. G. Diachenko.

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Translated by V. Potapchouck

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Sokolov, I.A., Stepchenkov, Y.A., Rogdestvenski, Y.V. et al. Approximate Evaluation of the Efficiency of Synchronous and Self-Timed Methodologies in Problems of Designing Failure-Tolerant Computing and Control Systems. Autom Remote Control 83, 264–272 (2022). https://doi.org/10.1134/S0005117922020084

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  • DOI: https://doi.org/10.1134/S0005117922020084

Keywords

  • hardware
  • failure tolerance
  • failure
  • synchronous circuit
  • self-timed circuit
  • dual-rail signal
  • C-element
  • indication