Abstract
The performance of a silicon stress-sensitive unijunction transistor is investigated. The transistor is classed as a stress-sensitive semiconductor lateral bipolar device with an S-type input (emitter) I-V characteristic. The optimal layout of the device and its basic parameters are determined. The device can serve as a basis for designing relaxation oscillators with the physically integrated function of mechanical stress-to-signal frequency conversion at the output.
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Translated from Zhurnal Tekhnichesko\(\overset{\lower0.5em\hbox{$\smash{\scriptscriptstyle\smile}$}}{l}\) Fiziki, Vol. 72, No. 4, 2002, pp. 66–71.
Original Russian Text Copyright © 2002 by Babichev, Kozlovskiy, Romanov, Sharan.
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Babichev, G.G., Kozlovskiy, S.I., Romanov, V.A. et al. A silicon stress-sensitive unijunction transistor. Tech. Phys. 47, 438–443 (2002). https://doi.org/10.1134/1.1470591
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DOI: https://doi.org/10.1134/1.1470591