Advertisement

Russian Microelectronics

, Volume 48, Issue 6, pp 381–393 | Cite as

Modeling the Charge Collection from a Track of an Ionizing Particle in Upset Hardened CMOS Trigger Elements

  • V. Ya. SteninEmail author
  • Yu. V. KatuninEmail author
Article

Abstract

The charge collection from tracks of ionizing nuclear particles in CMOS trigger elements of the STG DICE type in the picosecond range is simulated using the 3D TCAD and the results are presented. The transient processes at the charge collection from tracks are analyzed (i) in the STG DICE D-trigger used for the cells of static memory, (ii) in the RS STG trigger, and (iii) in the logic C-element based on the STG DICE trigger for the asynchronous CMOS logic. The simulation results of the charge collection by the pn junctions of both off and on transistors are presented. It is established that the charge collection from a track by MOS transistors begins in the off or on state and then transits to the charge collection in the inverse mode. The duration of the charge collection until the voltage extremum at the node of the trigger CMOS elements of the bulk 65-nm technology ranges from 5.5 to 17 ps, and the increments in the voltages of the extremums (maximums or minimums) at the nodes with respect to the voltages at the supply bus or at the common bus vary from 0.14 to 0.82 V. The duration of transistor occurrence in the inverse state ranges from 2 to 100 ps. The charge collection from tracks with the linear energy transfer (LET) of 60 MeV cm2/mg do not lead to the upset of the logical function of the elements for the tracks through the transistors of one group of the STG DICE trigger when there is sufficient spacing between the groups of transistors. The investigation results are oriented to designing systems which operate under the conditions of the action of single nuclear particles.

Keywords:

logic element modeling single nuclear particle noise immunity particle’s track trigger 

Notes

REFERENCES

  1. 1.
    Calin, T., Nicolaidis, M., and Velazco, R., Upset hardened memory design for submicron CMOS technology, IEEE Trans. Nucl. Sci., 1996, vol. 43, no. 6, pp. 2874–2878.CrossRefGoogle Scholar
  2. 2.
    Katunin, Yu.V., Stenin, V.Ya., and Stepanov, P.V., Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles, Russ. Microelectron., 2014, vol. 43, no. 2, pp. 112–124.CrossRefGoogle Scholar
  3. 3.
    Stenin, V.Ya., Simulation of the characteristics of the DICE 28-nm CMOS cells in unsteady states caused by the effect of single nuclear particles, Russ. Microelectron., 2015, vol. 44, no. 5, pp. 324–334.CrossRefGoogle Scholar
  4. 4.
    Stenin, V.Ya., Katunin, Yu.V., and Stepanov, P.V., Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups, Russ. Microelectron., 2016, vol. 45, no. 6, pp. 419–432.CrossRefGoogle Scholar
  5. 5.
    Seifert, N., Gill, B., Foley, K., and Relangi, P., Multi-cell upset probabilities of 45 nm high-k + metal gate SRAM devices in terrestrial and space environments, in Proceedings of IEEE International Reliability Physics Symposium,2008, pp. 181–186.Google Scholar
  6. 6.
    Warren, K.M., Stenberg, A.L., Black, J.D., Weller, R.A., Reed, R.A., Mendenhall, M.H., Schrimpf, R.D., and Massengill, L.W., Heavy ion testing and single-event upset rate prediction considerations for a DICE flip-flop, IEEE Trans. Nucl. Sci., 2009, vol. 56, no. 6, pp. 3130–3137.CrossRefGoogle Scholar
  7. 7.
    Seifert, N.P., Ambrose, V., Shi, Q., Allmon, R., Recchia, C., Mukherjee, S., Nassif, N., Krause, J., Pickholtz, J., and Balasubramanian, A., On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies, in Proceedings of IEEE International Reliability Physics Symposium,2010, pp. 188–197.Google Scholar
  8. 8.
    Stenin, V.Ya. and Cherkasov, I.G., Memory-cell layout as a factor in the single-event-upset susceptibility of submicron DICE CMOS SRAM, Russ. Microelectron., 2011, vol. 40, no. 3, pp. 170–175.CrossRefGoogle Scholar
  9. 9.
    Toure, G., Hubert, G., Castellani-Coulie, K., Duzellier, S., and Portal, J.-M., Simulation of single and multi-node collection: impact on SEU occurrence in nanometric SRAM cells, IEEE Trans. Nucl. Sci., 2011, vol. 58, no. 3, pp. 862–869.CrossRefGoogle Scholar
  10. 10.
    Lilja, K., Bounasser M., Wen S., Wong R., Holst J., Gaspard N., Jagannathan S., Loveless D., and Bhuva B., Single event performance and layout optimization of flip-flops in a 28-nm bulk technology, IEEE Trans. Nucl. Sci., 2013, vol. 60, no. 4, pp. 2782–2788.CrossRefGoogle Scholar
  11. 11.
    Massengill, L.W., Bhuva, B.L., Holman, W.T., Alles, M.L., and Loveless, T.D., Technology scaling and soft reliability, in Proceedings of IEEE International Reliability Physics Symposium,2012, pp. 3.C.1.1–3.C.1.7.Google Scholar
  12. 12.
    Gaspard, N., Jagannathan, S., Diggins, Z., McCurdy, M., Loveless, T.D., Bhuva, B.L., Massengill, L.W., Holman, W.T., Oates, T.S., Fang, Y-P., Wen, S.-J., Wong, R., Lilja, K., and Bounasser, M., Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS, in Proceedings of IEEE International Reliability Physics Symposium,2013, pp. SE.6.1–SE.6.5.Google Scholar
  13. 13.
    Stenin, V.Ya. and Stepanov, P.V., Basic memory elements using DICE cells for fault-tolerant 28 nm CMOS RAM, Russ. Microelectron., 2015, vol. 44, no. 6, pp. 368–379.CrossRefGoogle Scholar
  14. 14.
    Baze, M.P., Hughlock, B., Wert, J., Tostenrude, J., Massengill, L., Amusan, O., Lacoe, R., Lilja, K., and Johnson, M., Angular dependence of single-event sensitivity in hardened flip/flop design, IEEE Trans. Nucl. Sci., 2008, vol. 55, no. 6, pp. 3295–3301.CrossRefGoogle Scholar
  15. 15.
    Loveless, T.D., Jagannathan, S., Reece, T., Chetia, J., Bhuva, B.L., McCurdy, M.W., Massengill, L.W., Wen, S.-J., Wong, R., and Rennie, D., Neutron- and proton-induced single event upsets for D- and DICE-flip/flop designs at a 40 nm technology node, IEEE Trans. Nucl. Sci., 2011, vol. 58, no. 3, pp. 1008–1014.CrossRefGoogle Scholar
  16. 16.
    Uznanski, S., Gasiot, G., Roche, P., Tavernier, C., and Autran, J.-L., Single event upset and multiple cell upset modeling in commercial bulk 65-nm CMOS SRAMs and flip-flops, IEEE Trans. Nucl. Sci., 2010, vol. 57, no. 4, pp. 1876–1883.CrossRefGoogle Scholar
  17. 17.
    Giot, D., Roche, P., Gasiot, G., Autran, J.-L., and Harboe-Sorensen, R., Heavy ion testing and 3D simulations of multiple cell upset in 65 nm standard SRAMs, IEEE Trans. Nucl. Sci., 2008, vol. 55, no. 4, pp. 2048–2054.CrossRefGoogle Scholar
  18. 18.
    Wang, T., Xiao, L., and Huang, Q., Simulation study of single event effect for different N-well and deep-N-well doping in 65 nm triple-well CMOS devices, in Proceedings of International Conference on Optoelectronics and Microelectronics,2012, pp. 505–509.Google Scholar
  19. 19.
    Artola, L., Hubert, G., Duzellier, S., and Bezerra, F., Collected charge analysis for a new transient model by TCAD simulation in 90 nm technology, IEEE Trans. Nucl. Sci., 2010, vol. 57, no. 4, pp. 1869–1875.CrossRefGoogle Scholar
  20. 20.
    Katunin, Yu.V. and Stenin, V.Ya., Simulation of single event effects in STG DICE memory cells, Russ. Microelectron., 2018, vol. 47, no. 1, pp. 20–33.CrossRefGoogle Scholar
  21. 21.
    Katunin, Yu.V. and Stenin, V.Ya., The STG DICE cell with the decoder for reading data in steady and unsteady states for hardened SRAM, in IEEE Xplore (Conference Section, RADECS-2017), e-book, 2019, pp. 171–178.Google Scholar
  22. 22.
    Stenin, V.Ya. and Katunin, Yu.V., Simulation the effects of single nuclear particles on STG RS triggers with transistors spacing into two groups, Russ. Microelectron., 2018, vol. 47, no. 6, pp. 407–414.CrossRefGoogle Scholar
  23. 23.
    Katunin, Yu.V. and Stenin, V.Ya., Logical C-element on STG DICE trigger for asynchronous digital devices resistant to single nuclear particles, Russ. Microelectron., 2019, vol. 48, no. 3, pp. 143–156.CrossRefGoogle Scholar
  24. 24.
    Katunin, Yu.V. and Stenin, V.Ya., The element of matching on an STG DICE cell for an upset tolerant content addressable memory, Russ. Microelectron., 2018, vol. 47, no. 2, p. 142–156.CrossRefGoogle Scholar
  25. 25.
    Garg, R. and Khatri, S.P., Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations, New York: Springer, 2010, pp. 194–205.CrossRefGoogle Scholar
  26. 26.
    Nicolaidis, M., Soft Errors in Modern Electronic Systems, New York: Springer, 2011, pp. 35–37.CrossRefGoogle Scholar

Copyright information

© Pleiades Publishing, Ltd. 2019

Authors and Affiliations

  1. 1.Scientific Research Institute of System Analysis, Russian Academy of SciencesMoscowRussia
  2. 2.National Research Nuclear University MEPhIMoscowRussia

Personalised recommendations