Russian Microelectronics

, Volume 47, Issue 7, pp 487–493 | Cite as

TCAD Simulation of Dose Radiation Effects in Sub-100-nm High-κ MOS Transistor Structures

  • K. O. PetrosyantsEmail author
  • D. A. Popov
  • D. V. Bykov


The sub-100-nm CMOS process with a high-κ gate dielectric is one of the key technologies for the fabrication of digital, analog, and RF VLSI circuits and on-chip systems. The influence of ionizing radiation on 45-nm MOS transistors with a high-κ dielectric fabricated using the bulk-silicon and SOI technologies is simulated. Effects induced by the substitution of SiO2 with a high-κ dielectric are noted. The processes of selection and tuning of physical models for the simulation of high-κ MOS transistors in the Sentaurus TCAD are outlined. A set of new physical semiempirical models introducing the dependence of radiation-sensitive parameters (carrier lifetime, carrier mobility, charge density in the bulk of SiO2 and HfO2 and at the HfO2/Si interfaces) on the irradiation dose is developed. Nanoscale bulk and SOI MOS transistors with a high-κ dielectric are simulated. It is demonstrated that an increase in the drain current after irradiation in nanoscale SOI structures is induced by the charge accumulation in the side oxide. An acceptable fit between the simulation results and the experimental data is obtained. The simulation results confirm that the leakage current is suppressed (compared to common MOS transistors with SiO2) in sub-100-nm MOS transistors with a high-κ dielectric. However, the other important parameters of sub-100-nm MOS transistors with a high-κ dielectric are more sensitive to ionizing radiation.


high-κ dielectric MOS transistors SOI TCAD ionizing radiation 



This study was supported financially by the Ministry of Education and Science of Russia (project no. 8.9382.2017/8.9).


  1. 1.
    Jan, C.H., Agostinelli, M., Deshpande, H., et al., RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications, in Proceedings of IEEE International Electron Devices Meeting, 2010, pp. 27.2.1–27.2.4.Google Scholar
  2. 2.
    Lee, S., Kim, J., Jagannathan, B., et al., SOI CMOS technology with 360 GHz fT NFET, 260 GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications, in Proceedings of IEEE Symposium on VLSI Technology, 2007, pp. 54–55.Google Scholar
  3. 3.
    Lee, S., Jagannathan, B., Narasimha, S., et al., Record RF performance of 45-mn SOICMOS technology, in Proceedings of IEEE International Electron Devices Meeting, 2007, pp. 255–258.Google Scholar
  4. 4.
    Appswamy, A., Jun, B., Diestelhorst, R., et al., The effects of proton irradiation on 90 nm strained Si CMOS on SOI devices, in Proceedings of IEEE Radiation Effects Data Workshop, 2006, pp. 62–65.Google Scholar
  5. 5.
    Madan, A., Verma, R., Arora, R., et al., The enhanced role of shallow-trench isolation in ionizing radiation damage of 65 nm RF-CMOS on SOI, IEEE Trans. Nucl. Sci., 2009, vol. 56, pp. 3256–3261.CrossRefGoogle Scholar
  6. 6.
    Arora, R., Zhang, E., Seth, S., et al., Trade-offs between RF performance and total-dose tolerance in 45-nm RF-CMOS, IEEE Trans. Nucl. Sci., 2011, vol. 57, pp. 2830–2837.CrossRefGoogle Scholar
  7. 7.
    Arora, R., Fleetwood, Z.E., En Xia Zhang, et al., Impact of technology scaling in sub-100 nm nMOSFETs on total-dose radiation response and hot-carrier reliability, IEEE Trans. Nucl. Sci., 2014, vol. 61, no. 3, pp. 1426–1432.CrossRefGoogle Scholar
  8. 8.
    Rana, A.K., Chand, N., and Kapoor, V., TCAD based analysis of gate leakage current for high-k gate stack MOSFET, ACEEE Int. J. Commun., 2011, vol. 2, no. 1, pp. 5–8.Google Scholar
  9. 9.
    Chander, S., Singh, P., and Baishya, S., Optimization of direct tunneling gate leakage current in ultrathin gate oxide FET with High-K dielectrics, Int. J. Recent Develop. Eng. Technol., 2013, no. 1, pp. 24–30.Google Scholar
  10. 10.
    Shen, C., Yang, L.T., Samudra, G., and Yeo, Y.C., A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnel-FET, Solid-State Electron., 2011, vol. 57. P. 23–30.CrossRefGoogle Scholar
  11. 11.
    Yadav, S., Srivastava, A., Rahul, J., and Jha, K.K., TCAD assessment of nonconventional dual insulator double gate MOSFET, in Proceedings of the International Conference on Devices, Circuits and Systems ICDCS, 2012, pp. 462–465.Google Scholar
  12. 12.
    Shashank, N., Basak, S., and Nahar, R.K., Design and simulation of nano scale high-k based MOSFETs with poly silicon and metal gate electrodes, Int. J. Adv. Technol., 2010, vol. 1, no. 2, pp. 252–261.Google Scholar
  13. 13.
    Shashank, N., Singh, V., Taube, W.R., and Nahar, R.K., Role of interface charges on high-k based poly-Si and metal gate nano-scale MOSFETs, J. Nano- Electron. Phys., 2011,vol. 3. no. 1, pp. 937–941.Google Scholar
  14. 14.
    Petrosyants, K.O. and Popov, D.A., High-k gate stacks influence on characteristics of nano-scale MOSFET structures, in Proceedings of the 2nd International Conference on Modeling, Identification and Control MIC 2015, Paris, 2015, pp. 174–176.Google Scholar
  15. 15.
    Petrosyants, K.O. and Popov, D.A., TCAD simulation of total ionization dose response of 45 nm high-k MOSFETs on bulk silicon and SOI substrate, in Proceedings of the 24th European Conference on Radiation and its Effects on Components and Systems-2015 RADECS 2015, Moscow, Russia, Sept. 14–18, Piscataway: Inst. Electrical and Electron. Eng., 2015, pp. 27–30.Google Scholar
  16. 16.
    Petrosjanc, K.O., Popov, D.A., Sambursky, L.M., and Kharitonov, I.A., Leakage currents analysis of 45 nm MOSFET structure with high-k dielectric by TCAD, Izv. Vyssh. Uchebn. Zaved., Elektron., 2015, no. 1, pp. 38–43.Google Scholar
  17. 17.
    Rezzak, N., Total ionizing dose effects in advanced CMOS technologies, PhD Dissertation, Nashville, TN: Vanderbilt Univ., 2012.Google Scholar
  18. 18.
    TCAD Sentaurus User Manual J-2014.09, Synopsys.Google Scholar
  19. 19.
    Gusev, E.P., Cartier, E., Buchanan, D.A., et al., Ultrathin high-k metal oxides on silicon: processing, characterization and integration issues, Microelectron. Eng., 2001, vol. 59, nos. 1–4, pp. 341–349.CrossRefGoogle Scholar
  20. 20.
    Vasileska, D., The influence of space quantization effects on the threshold voltage, inversion layer and total gate capacitances in scaled Si-MOSFETs, J. Model. Simul. Microsyst., 1999, vol. 1, no. 1, pp. 49–56.Google Scholar
  21. 21.
    Zebrev, G.I., Fizicheskie osnovy kremnievoi nanoelektroniki (Physical Principles of Silicon Nanoelectronics), Moscow: BINOM, Labor. Znalii, 2011.Google Scholar
  22. 22.
    Young, C.D., Bersuke, G., Brown, G.A., et al., Charge trapping in MOCVD hafnium-based gate field dielectric stack structures and its impact on device performance, in Proceedings of the IEEE International Integrated Reliability Workshop, 2003, pp. 28–35.Google Scholar
  23. 23.
    Miyata N., Study of direct-contact HfO2/Si interfaces, Materials, 2012, vol. 5. pp. 512–527.CrossRefGoogle Scholar
  24. 24.
    Guillaumot, B., Garros, X., Lime, F., et al., 75 nm Damascene Metal Gate and high-k Integration for Advanced CMOS devices, in IEDM Tech. Dig., 2002, pp. 355–358.Google Scholar
  25. 25.
    Zhu, W.J., Ma, T.P., Zafar, S., and Tamagawa, T., Charge trapping in ultrathin hafnium oxide, IEEE Electron Dev. Lett., 2002, vol. 23, no. 10, pp. 597–599.CrossRefGoogle Scholar
  26. 26.
    Cheng, Y., Ding, M., Wu, X., et al., Irradiation effect of HfO2 MOS structure under gamma-ray, in Proceedings of the ICSD, Bologna, Italy, 2013, pp. 764–767.Google Scholar
  27. 27.
    Zhao, C.Z., Taylor, S., Werner, M., et al., High-k materials and their response to gamma ray radiation, J. Vac. Sci. Technol. B, 2009, vol. 27, no. 1, pp. 411–415.CrossRefGoogle Scholar
  28. 28.
    Dixit, S.K., Zhou, X.J., Schrimpf, R.D., et al., Radiation induced charge trapping in ultrathin HfO2-based MOSFETs, IEEE Trans. Nucl. Sci., 2007, vol. 54, no. 6, pp. 1883–1889.CrossRefGoogle Scholar
  29. 29.
    Hamamura, H., Ishida, T., Mine, T., et al., Electron trapping characteristics and scalability of HfO2 as a trapping layer in SONOS-type flash memories, in Proceedings of the IEEE International Reliability Physics Symposium, 2008, pp. 412–416.Google Scholar
  30. 30.
    Sanchez Esqueda, I., Barnaby, H.J., and Kin, M.P., Compact modeling of total ionizing dose and aging effects in MOS technologies, IEEE Trans. Nucl. Sci., 2015, vol. 62, no. 4, pp. 1501–1515.CrossRefGoogle Scholar
  31. 31.
    Liu, S.T., Hurst, A.L., McMarr, P., et al., Total dose radiation response of a 45 nm SOI technology, in Proceedings of the SOI Conference, San Diego, USA, 2010, pp. 1–2.Google Scholar
  32. 32.
    Gaillardi, M., Martinez, M., Paillet, P., et al., Impact of SOI substrate on the radiation response of ultrathin transistors down to the 20 nm node, IEEE Trans. Nucl. Sci., 2013, vol. 60, no. 4, pp. 2583–2589.CrossRefGoogle Scholar

Copyright information

© Pleiades Publishing, Ltd. 2018

Authors and Affiliations

  • K. O. Petrosyants
    • 1
    • 2
    Email author
  • D. A. Popov
    • 1
  • D. V. Bykov
    • 1
  1. 1.National Research University Higher School of EconomicsMoscowRussia
  2. 2.Scientific Research Institute of Advanced Materials and TechnologiesMoscowRussia

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