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Russian Microelectronics

, Volume 43, Issue 2, pp 102–111 | Cite as

Limitations and prospects of using the two-phase CMOS logics in upset-immune sub-100-nm VLSIs

  • V. Ya. Stenin
Article

Abstract

The upset immunity of CMOS inverters with a two-phase structure to the effect of single nuclear particles for inverters with 65-nm and 45-nm design rules substantially depends on the capacitive coupling of their differential inputs (outputs). To evaluate the upset immunity, threshold characteristics are suggested, which associate the threshold values of critical charges with the corresponding threshold values of the capacity of the differential coupling. With the capacities of the differential coupling lower than the threshold values, the critical charges of two-phase CMOS inverters exceed the critical charges of the conventional CMOS logics by a factor of more than 10. Critical charges have lower values under the effect of current pulses with small constant rise and fall times.

Keywords

Current Pulse RUSSIAN Microelectronics Upset Immunity Phase Inverter Critical Charge 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Pleiades Publishing, Ltd. 2014

Authors and Affiliations

  1. 1.Scientific Research Institute of System AnalysisRussian Academy of SciencesMoscowRussia
  2. 2.National Research Nuclear University MEPhIMoscowRussia

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