Advertisement

Russian Microelectronics

, Volume 41, Issue 1, pp 59–70 | Cite as

Estimating energy consumption in logical CMOS circuits based on their switching activity

  • P. N. Bibilo
  • N. A. Kirienko
Article

Abstract

The relationship between energy consumption and switching activity of logic circuits built of CMOS-based gates from the library of custom VLSIC designing. The switching activity of the logic circuit, i.e., total number of switched transistors integrated into the circuit is counted for a certain sequence of input signals sets. It is suggested to estimate energy consumption in the synthesized logic CMOS circuit based on the parameter of its switching activity, thus, avoiding time-consuming circuit simulation. The results of experiments on various ways of estimating energy consumption in combinational circuits at the stage of logical designing are described and compared with the results of circuit simulation.

Keywords

Logical Gate RUSSIAN Microelectronics Logical Circuit Switching Activity Circuit Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Rabai, J.M., Chandrakasan, A., and Nikolich, B., Tsifrovye integral’nye skhemy (Digital Integrated Circuits), Moscow: OOO “I.D. Vil’yams”, 2007.Google Scholar
  2. 2.
    Gres’, T., Solov’ev, V.V., and Bulatova, I.R., Simulation of Consumption in Elements of Digital Devices, Avtometriya, 2009, vol. 45, no. 5, pp. 105–114.Google Scholar
  3. 3.
    Bibilo, P.N., Sintez Kombinatsionnykh PLM-Struktur dlya SBIS (Synthesis of Combinational PLA Structures for VLSIs), Minsk: Nauka i Tekhnika, 1992.Google Scholar
  4. 4.
    Kirienko, N.A., Algorithm of Logical Modeling of the Combinational Circuit from Library Elements, in Tanaevskie chteniya: doklady Chetvertoi Mezhdunarodnoi nauchnoi konferentsii (Tananaev Readings: Reports of the Fourth Int. Sci. Conf.), Minsk: OIPI NAN Belarusi, 2010, pp. 68–71.Google Scholar
  5. 5.
    Toropov, N.R., Transformation of Multilevel Combination Network into Tow-Level, Logich. Proektir., 2000, no. 5, pp. 4–14.Google Scholar
  6. 6.
    Bibilo, P.N., Basil’kova, I.V., Kardash, S.N., et al., Custom Logic: A Toolkit for the Design of VLSI Custom Control MOS Logic, Russ. Mikroelektron., 2004, vol. 33, no. 5, p. 310.CrossRefGoogle Scholar
  7. 7.
    Suvorova, E.A. and Sheinin, Yu.E., Proektirovanie tsifrovykh sistem na VHDL (Design of Digital Systems Using VHDL), St. Petersburg: BKhV-Peterburg, 2003.Google Scholar
  8. 8.
    Berkeley PLA test set [Electronic resource]. Access Mode: http://www1.cs.columbia.edu/~cs4861/sis/espresso-examples/. Access date: 03.05.2006
  9. 9.
    Bibilo, P.N., Sistemy proektirovaniya integral’nykh skhem na osnove yazyka VHDL. StateSAD, ModelSim, LeonardoSpectrum (Systems for Design of Integrated Circuits Based on the VHDL Language. StateCAD, ModelSim, LeonardoSpectrum), Moscow: SOLON-Press, 2005.Google Scholar
  10. 10.
    Zakrevskii, A.D., Minimization of the Exhaustion of Oriented Pairs, in Tanaevskie chteniya: doklady Chetvertoi Mezhdunarodnoi nauchnoi konferentsii (Tananaev Readings: Reports of the Fourth Int. Sci. Conf.), Minsk: OIPI NAN Belarusi, 2010, pp. 58–62.Google Scholar

Copyright information

© Pleiades Publishing, Ltd. 2012

Authors and Affiliations

  • P. N. Bibilo
    • 1
  • N. A. Kirienko
    • 1
  1. 1.Joint Institute of Problems of Information ScienceNational Academy of Science of BelarusMinskBelarus

Personalised recommendations