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Automated Generation of Machine Instruction Decoders

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Abstract

A method for the automated generation of machine instruction decoders for a wide range of processor architectures that uses the target architecture assembler is proposed. A software tool based on this method is implemented and tested on a number of microcontrollers, such as PIC16F877A, AVR, Tricore, and H8/300H.

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Author information

Correspondence to N. Yu. Fokina or M. A. Solovev.

Additional information

Translated by A. Klimontovich

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Fokina, N.Y., Solovev, M.A. Automated Generation of Machine Instruction Decoders. Program Comput Soft 45, 390–397 (2019). https://doi.org/10.1134/S0361768819070065

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