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Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

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Abstract

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper develops a framework for dynamic parameterization and applies it to MPEG-4 motion estimation. A novel motion estimation architecture facilitates the dynamic variation of parameters to achieve power-compression tradeoffs. Our work shows that parameter variation in motion estimation helps achieve power reduction by an order of magnitude, trading off higher compression for lower power. The magnitude of the tradeoffs depends on the input signal variation. The monitoring of input and output signal statistics and subsequent variation of parameters is accomplished by a hardware controller. To provide the controller with a model of the parameter space and corresponding measures in terms of power and performance, a configuration sample space graph is developed. This graph identifies the parameters which present the best power-performance tradeoffs. The controller samples the operating environment to select the appropriate parameters. This reduces the average power consumption by 40% for 2% loss in compression. Four other signal dependent computations: (1) 2D Discrete Cosine Transform, (2) Lempel-Ziv lossless compression, (3) 3D graphics light rendering, and (4) Viterbi decoding are briefly discussed to demonstrate the applicability of dynamic reconfiguration.

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References

  1. J. Rabaey, “Reconfigurable Processing: The Solution to Low-Power Programmable DSP,” in Proceedings, International Conference on Acoustics, Speech and Signal Processing, Munich, Germany, April 1997, pp. 275-278.

  2. H. Zhang, V. Prabhu, V. George, M. Wan, M. Benes, A. Abnous, and J. Rabaey, “A 1 V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications,” in Proceedings, International Solid State Circuit Conference, San Francisco, CA, Feb. 2000, pp. 68-69.

  3. P. Kuhn, Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation. Netherlands: Kluwer Academic Publications, 1999.

    Book  MATH  Google Scholar 

  4. J. Liang, S. Swaminathan, and R. Tessier, “aSOC: A Scalable, Single-Chip Communications Architecture,” in Proceedings, IEEE International Conference on Parallel Architectures and Compilation Techniques, Philadelphia, PA, Oct. 2000.

  5. A. Laffely, J. Liang, P. Jain, N. Weng, W. Burleson, and R. Tessier, “Adaptive System on a Chip (aSoC) for Low-Power Signal Processing,” in Proceedings, Thirty-Fifth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Nov. 2001.

  6. P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI Architectures for Video Compression—A Survey,” Proceedings of the IEEE, vol. 83, no. 2, 1995, pp. 220-248.

    Article  Google Scholar 

  7. M. Bhardwaj, R. Min, and A. Chandrakasan, “Quantifying and Enhancing Power-Awareness of VLSI Systems,” IEEE Transactions on VLSI Systems, 2001.

  8. T. Nishikawa, M. Takahashi, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H. Yamamoto, T. Fujiyoshi, Y. Matsumoto, O. Yamagishi, T. Samata, A. Asano, T. Terazawa, K. Ohmori, J. Shirakura, Y. Watanabe, H. Nakamura, S. Minami, T. Kuroda, and T. Furuyama, “A 60 MHz 240 mW MPEG-4 Video-Phone LSI with 16 Mb Embedded DRAMToshiba,” in Proceedings, International Solid State Circuit Conference, San Francisco, CA, Feb. 2000.

  9. T. Hashimoto, S. Kuromaru, M. Matsuo, H. Nakajima, Y. Kohashi, K. Ishida, T. Mori-iwa, M. Ohashi, K. Hashimoto, T. Yonezawa, M. Hamada, T. Nakamura, M. Toujima, Y. Sugisawa, T. Kondo, H. Otsuki, M. Arita, H. Fujimoto, H. Toida, and H. Ito, “A 90 mW MPEG4 Video Codec LSI with the Capability for Core Profile,” in Proceedings, International Solid State Circuit Conference, San Francisco, CA, Feb. 2001.

  10. V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards—Algorithms and Architectures, 2nd edition, Norwell: Kluwer Academic Publishers, 1997.

    Book  Google Scholar 

  11. T. Xanthopoulos and A.P. Chandrakasan, “A Low-Power DCT Core Using Adaptive Bitwidth and Arithmetic Activity Exploiting Signal Correlations and Quantization,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, 2000.

  12. S. Venkatraman, “A Power-Aware Synthesizable Core for the Descrete Cosine Transform,” Thesis, M.S. E.C.E., University of Massachusetts Amherst, Sept. 2001.

  13. B. Jung and W. Burleson, “VLSI Algorithm, Architecture and Implementation for High-Speed Lempel-Ziv Data Compression,” IEEE Transactions on VLSI Systems, Sept. 1998.

  14. B. Jung, “VLSI Arrays for Source Coding in Wireless Local Area Networks,” Dissertation, Ph.D. E.C.E, University of Massachusetts Amherst, Feb. 1997.

  15. J. Euh and W. Burleson, “Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering,” in Proceedings, Power-Aware Computing Symposium, Cambridge, MA, 2000.

  16. A. Viterbi, “Error Bound for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Transactions on Information Theory, vol. 13, April 1967, pp. 260-269.

    Article  MATH  Google Scholar 

  17. J. Omura, “On the Viterbi Decoding Algorithm,” IEEE Transactions on Information Theory, vol. 15, April 1969, pp. 177-179.

    Article  MathSciNet  Google Scholar 

  18. F. Chan and D. Haccoun, “Adaptive Viterbi Decoding of Convolutional Codes over Memoryless Channels,” IEEE Transactions on Communications, vol. 45, Nov. 1997, pp. 1389-1400.

    Article  Google Scholar 

  19. S. Simmons, “Breadth-First Trellis Decoding with Adaptive Effort,” IEEE Transactions on Communications, vol. 38, Cambridge, MA, 2000.

  20. S. Swaminathan, R. Tessier, D. Goeckel, and W. Burleson, “A Dynamically Reconfigurable Adaptive Viterbi Decoder,” in Proceedings, 10th International ACM/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, California, Feb. 2002.

  21. Xilinx Corporation, Virtex II data sheet, 2001. http://www.xilinx.com

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Authors and Affiliations

  1. University of Massachusetts Amherst, 309 Knowles Engineering Building, Amherst, MA, 01003, USA

    Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier & Dennis Goeckel

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  1. Prashant Jain
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  2. Andrew Laffely
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  3. Wayne Burleson
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  4. Russell Tessier
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  5. Dennis Goeckel
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Jain, P., Laffely, A., Burleson, W. et al. Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 36, 27–40 (2004). https://doi.org/10.1023/B:VLSI.0000008068.26922.0b

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  • DOI: https://doi.org/10.1023/B:VLSI.0000008068.26922.0b

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