Abstract
In this paper we present a hardware implementation of the Discrete Stochastic Arithmetic (DSA) which is based on CESTAC (Controle et Estimation STochastique des Arrondis de Calculs), a method of controlling round-off errors in floating-point scientific computations. Real-time software implementation of this method suffers from computation bottlenecks. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed architecture is based on a Stochastic Floating-Point Unit (SFPU) which performs discrete stochastic operations. This SFPU has been integrated in a coprocessor, used in a complete System on Chip (SoC).
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References
ANSI/IEEE Std 754–1985, IEEE standard for binary floating-point arithmetic (1985).
J.-M. Chesneaux, Study of the computing accuracy by using probabilitic approach, in: Contribution to Computer Arithmetic and Self-Validating Numerical Methods, ed. C. Ulrich (1990) pp. 19–30.
J.-M. Chesneaux, L'arithmétique stochastique et le logiciel CADNA, Habilitation à diriger des recherches, Université Pierre et Marie Curie (November 1995).
M.S. Cohen, T.E. Hull and V.C. Hamarcher, CADAC: A controlled-precision decimal arithmetic unit, IEEE Trans. Comput. 32 (1983) 370–377.
A. Greiner and al ALLIANCE, A complet set of CAD tools for teaching VLSI design, in: Third EuroChip Workshop, 1992, http://www-asim.lip6.fr/alliance.
W. Kahan, The Improbability of Probabilistic Error Analyses for Numerical Computations, UCB Statistics Colloquium (Evans Hall edition, 1996).
OMI 324, OMI/PI-Bus specification, PI-BUS Rev. 0.3d (1994).
F. Pétrot, Cycle accurate system simulation, in: Medea-Esprit Conference, November 1999.
M. Pichat and J. Vignes, Ingénierie du Contrôle de la Précision des Calculs sur Ordinateur (Technip, 1993).
S.M. Rump, How reliable are results of computers, in: Jahrbuch Uberblicke Mathematik (1983) pp. 163–168.
M.J. Schulte and E.E. Swartzlander Jr., Hardware design and arithmetic algorithms for a variable-precision, interval arithmetic coprocessor, in: Proc. of the 12th Symposium on Computer Arithmetic, 1995, pp. 163–171.
J. Vignes, Zéro mathématique et zéro informatique, La Vie des Sciences, C. R. Acad. Sci. Paris 4(1) (1987) 1–13.
J. Vignes, Review on stochastic approach to round-off error analysis and its applications, Math. Comput. Simulation 30 (1988) 481–491.
J. Vignes, A stochastic arithmetic for reliable scientific computation, Math. Comput. Simulation 35 (1993) 233–261.
J. Vignes and M. La Porte, Error analysis in computing, in: Information Processing '74 (North-Holland, Amsterdam, 1974).
Virtual Sockets Interface Alliance, VSI ALliance Virtual Component Interface Standard (OCB design working group edition, November 2000).
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Avot-Chotin, R., Mehrez, H. Hardware Implementation of Discrete Stochastic Arithmetic. Numerical Algorithms 37, 21–33 (2004). https://doi.org/10.1023/B:NUMA.0000049455.07441.ee
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DOI: https://doi.org/10.1023/B:NUMA.0000049455.07441.ee