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Scaling MOSFETs to the Limit: A Physicists's Perspective

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Abstract

To circumvent its present practical limits—mainly gate leakage and poor performance—‘MOSFET scaling’ has taken a different meaning: Not simply shrinking the device, but changing its nature. Here it is suggested that long-range Coulomb interactions constitute a possible fundamental cause of the poor performance of sub-50 nm devices. Alternative device-designs and materials are briefly discussed from a transport-physics perpsective: High-κ insulators, transport in thin Si body (SOI and double-gate), along different crystal directions and on different materials. The major role played by the interfaces (surface plasmons and phonons, roughness, confinement) emerges as one of the most important common elements.

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  1. IBM Semiconductor Research and Development Center (SRDC), IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY, 10598, USA

    M.V. Fischetti

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Fischetti, M. Scaling MOSFETs to the Limit: A Physicists's Perspective. Journal of Computational Electronics 2, 73–79 (2003). https://doi.org/10.1023/B:JCEL.0000011402.54036.32

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