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Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints


This paper presents a methodology for automatically designing Instruction-Set Extensions in embedded processors. Many commercially available CPUs now offer the possibility of extending their instruction set for a specific application. Their tool chains typically support manual experimentations, but algorithms that can define the set of customised functional units most beneficial for a given applications are missing. Only a few algorithms exist but are severely limited in the type and size of operation clusters they can choose and hence reduce significantly the effectiveness of specialisation. A more general algorithm is presented here which selects maximal-speedup convex subgraphs of the application dataflow graph under fundamental microarchitectural constraints, and which improves significantly on the state of the art.

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Atasu, K., Pozzi, L. & Ienne, P. Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. International Journal of Parallel Programming 31, 411–428 (2003).

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  • customisable processors
  • instruction-set extensions
  • hardware/software codesign
  • automatic partitioning