Abstract
This article discusses hardware-oriented issues related to the compensation of channel distortions in packed-based mobile Orthogonal Frequency Division Multiplexing (OFDM) systems. The adopted evaluation approach relies upon Field-Programmable Gate Array (FPGA) prototyping. Depending on radio channel parameters and the modulation scheme, the required computation effort for the compensation of channel distortions can depict significant variations. In order to perform a trade-off analysis between complexity and performance, different compensation methods for channel distortions have been simulated within an OFDM simulation chain. Based on these results, hardware models have been created and prototyped onto a FPGA. The performance of the models with regard to the hardware efficiency is evaluated by integrating the prototyped components into the OFDM simulation chain. The hardware designs and simulations have been done according to the high-speed wireless LAN standard HiperLAN/2.
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Pionteck, T., Kabulepa, L.D. & Glesner, M. On the Rapid Prototyping of Equalizers for OFDM Systems. Design Automation for Embedded Systems 8, 283–295 (2003). https://doi.org/10.1023/B:DAEM.0000013063.88613.e0
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DOI: https://doi.org/10.1023/B:DAEM.0000013063.88613.e0