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Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method

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Abstract

A method of reducing the power consumption of a pseudorandom test pattern generator for scan-based built-in self-tests of digital devices is designed on the basis of formation of several test symbols in one operation cycle of the circuit.A new structure for low-power test pattern generators is described.

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Authors and Affiliations

  1. Belarussian State University of Informatics and Radioelectronics, Minsk, Belarus

    I. A. Murashko & V. N. Yarmolik

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  1. I. A. Murashko
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  2. V. N. Yarmolik
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Murashko, I.A., Yarmolik, V.N. Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method. Automation and Remote Control 65, 1265–1275 (2004). https://doi.org/10.1023/B:AURC.0000038729.41847.f0

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  • DOI: https://doi.org/10.1023/B:AURC.0000038729.41847.f0

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