Journal of Electronic Testing

, Volume 20, Issue 3, pp 315–323 | Cite as

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency

  • Debesh Kumar Das
  • Satoshi Ohtake
  • Hideo Fujiwara


This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all the techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware DL to uniquely identify a state appearing in a state register. The design of DL is universal. Test length and hardware overhead outperform the similar approaches.

ATPG scan and non-scan fault efficiency 


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Copyright information

© Kluwer Academic Publishers 2004

Authors and Affiliations

  • Debesh Kumar Das
    • 1
  • Satoshi Ohtake
    • 2
  • Hideo Fujiwara
    • 2
  1. 1.Department of Comp. Sc. and Engg.Jadavpur UniversityKolkataIndia
  2. 2.Graduate School of Information ScienceNara Institute of Science and TechnologyNaraJapan

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