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Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

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Abstract

High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. This paper reviews hardware and software techniques that alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be reduced if a high-capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation). Novel organizations for the register file based on clustering and hierarchical organization are necessary to meet the technology constraints. This paper proposes the used of a clustered organization and proposes an aggressive instruction scheduling technique that minimizes the negative effect of the limitations imposed by the register file organization.

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Authors and Affiliations

  1. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, U.S.A

    Javier Zalamea, Josep Llosa, Eduard Ayguadé & Mateo Valero

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  1. Javier Zalamea
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  2. Josep Llosa
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  3. Eduard Ayguadé
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  4. Mateo Valero
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Zalamea, J., Llosa, J., Ayguadé, E. et al. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. International Journal of Parallel Programming 32, 447–474 (2004). https://doi.org/10.1023/B:IJPP.0000042082.31819.6d

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