Abstract
In this paper the design of a 2 GHz direct-downconversion mixer for a UTRA/FDD receiver is presented. The mixer is implemented using a standard low-cost 0.25 μm, single-poly, six-metal CMOS process. An on-chip passive balun is used to generate a balanced RF input signal. In-house optimized device models are used for both active and passive components to achieve a voltage conversion gain of 12.8 dB, an iIP2 of 25 dBm, an iIP3 of −3.1 dBm, and a noise figure of 8 dB. The circuit provides I and Q signal path outputs while drawing 6 mA from a 2.5 V supply.
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Bøjer, J., Gentsch, M.B., Jensen, O.K. et al. An UTRA/FDD Direct-Downconversion Mixer in 0.25 μm CMOS. Analog Integrated Circuits and Signal Processing 38, 27–33 (2004). https://doi.org/10.1023/A:1025894105134
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DOI: https://doi.org/10.1023/A:1025894105134