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The Universal Configurable Block/Machine— An Approach for a Configurable SoC-Architecture

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Abstract

The universal configurable block/machine is a block-based approach for a configurable system-on-chip-(CSoC-) architecture. The programming model of the blocks is similar to microprocessor models, while the execution model supports configurable computing including reconfiguration. This is achieved by the microarchitecture of the blocks and an additional translation phase, resulting in three phases of overall program execution: fetching, translation and execution. These phases may act without strict coupling, simplifying the duplication of the executing part. The resulting hardware model is classified by four parameter: number of blocks, hyperblock sequencer, hyperblock scheduler and a set of block interconnections. The scheduler indicates that the model is capable of executing operating system work by scheduling hardware resources to threads or processes. This homogeneous CSoC may be used as compile-time defined inhomogeneous application-specific architecture. In this case the development process defines threads to run completely in one or more blocks solving partial problems and communicating to others. This enhances the flexibility and the optimization capabilities towards performance and/or real-time behavior.

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Authors and Affiliations

  1. University of Applied Sciences Nordhausen, Weinberghof 4, D-99734, Nordhausen, Germany

    Christian Siemers & Volker Winterstein

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  1. Christian Siemers
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  2. Volker Winterstein
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Siemers, C., Winterstein, V. The Universal Configurable Block/Machine— An Approach for a Configurable SoC-Architecture. The Journal of Supercomputing 26, 309–331 (2003). https://doi.org/10.1023/A:1025651132236

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