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Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures

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Cybernetics and Systems Analysis Aims and scope

Abstract

A mathematical model of programs, which is based on the concept of a hierarchical graph, is described. The model is used in the retargetable optimizing compiler NVRK-2 for microprocessor architectures with irregular very long instruction words (VLIWs). A formal description of a microprocessor with such an architecture is proposed and issues of code generation and analysis of microprocessors with VLIWs extended by a collection of instructions for signal processing and multimedia application are discussed. The problem of the computational speedup of the architectures being considered is also discussed.

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REFERENCES

  1. V. V. Voyevodin, “Mapping of problems of computing mathematics onto architectures of computer systems,” Vychisl. Metody i Programmirovanie, Vol. 1, 44-73 (2000).

    Google Scholar 

  2. V. A. Evstigneev,“ Some distinctive features of software with a long instruction word,” Programmirovanie, No. 2, 69-80 (1991).

  3. P. Marwedel and G. Goossens (eds.), Code Generation for Embedded Processors, Kluwer Academic, Dordrecht (1995), ISBN 0-7923-9577-8.

    Google Scholar 

  4. A. Yu. Doroshenko and D. V. Kuivashev, “The architecture of a modular cross-compiler for microprocessors with a very long instruction word,” Probl. Progr., Nos. 3-4, 122-134 (2000).

    Google Scholar 

  5. V. A. Evstigneev and V. N. Kas'yanov, Reducible Graphs and Graph Models in Programming [in Russian], IDMI, Novosibirsk (1999).

    Google Scholar 

  6. A. V. Aho, R. Sethi, and J. D. Ullman, Compilers: Principles, Techniques, and Tools, Addison-Wesley, Reading, Massachusetts (1986).

    Google Scholar 

  7. V. A. Evstigneev and V. N. Kas'yanov, “Optimizing transformations in parallelizing compilers,” Programmirovanie, No. 6, 12-26 (1996).

  8. D. F. Bacon, S. L. Graham, and O. J. Sharp, “Compiler transformations for high-performance computing,” ACM Computing Surveys, 26, No. 4, 345-420 (1994).

    Google Scholar 

  9. G. I. Shpakovskii, Organization of Parallel Computers and Superscalar Processors [in Russian], Belgosuniversitet, Minsk (1996).

    Google Scholar 

  10. Analog Devices: ADSP-21060 User Manual (1998), http://www.analog.com/publications/documentation/.

  11. TMS Cx80 User Manual, http://www.ti.com.

  12. A. V. Frolov, “Determination and use of oriented sections of real-word graphs of algorithms,” Programmirovanie, No. 4, 71-80 (1997).

  13. A. S. Antonov and Vl. V. Voyevodin, “Efficient adaptation of sequential programs for modern vector-pipelined and massively parallel supercomputers,” Programmirovanie, No. 4, 37-51 (1996).

  14. A. W. Lim and M. S. Lam, “Maximizing parallelism and minimizing synchronization with affine partitions,” in: Conf. Record of the 24th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, New York (January 1997).

  15. Yu. A. Frantsuzov, “Construction of estimates for the problem of scheduling codes in pipeline processors,” Programmirovanie, No. 4, 57-71 (1993).

  16. S. V. Skvortsov, “Code optimization for superscalar processors with the use of disjunctive graphs,” Programmirovanie, No. 2, 41-52 (1996).

  17. Yu. A. Frantsuzov, “A review of methods of parallelizing codes and pipelining programs,” Programmirovanie, No. 3, 16-37 (1992).

  18. V. Allan, R. Jones, R. Lee, and S. Allan, “Software pipelining,” ACM Computing Surveys, 27, No. 3, 367-432 (1995).

    Google Scholar 

  19. M. W. Hall, B. R. Murphy, and S. P. Amarasinghe, “Interprocedural analysis for parallelization: Design and experience,” in: Proc. 7th SIAM Conf. on Parallel Processing for Scientific Computing, New York (February 1995).

  20. V. A. Evstigneev and V. A. Serebryakov,“ Methods of interprocedural analysis (a review),” Programmirovanie, No. 3, 4-15 (1992).

  21. S. Liao, S. Devadas, K. Keutzer, et al., “Code generation and optimization techniques for embedded digital signal processors,” in: G. De Micheli and M. Sami (eds.), Hardware/Software Co-Design, Kluwer Academic, Dordrecht (1995), pp. 599-604.

    Google Scholar 

  22. P. Marwedel, “The MIMOLA design system: Tools for design of digital processors,” in: Proc. 21th Design Autom. Conf. (1984), pp. 587-593.

  23. “FlexWare: A flexible firmware development environment for embedded systems,” in: P. Paulin, et. al. (eds.), Code Generation for Embedded Processors, Kluwer Academic, Dordrecht (1995), pp. 67-84.

  24. “CHESS: Retargetable code generation for embedded DSP processors,” in: D. Lanneer, et al. (eds.), Code Generation for Embedded Processors, Kluwer Academic, Dordrecht (1995), pp. 85-102.

  25. “An ILP-Based approach to code generation,” in: T. Wilson, et al. (eds.), Code Generation for Embedded Processors, Kluwer Academic, Dordrecht (1995), pp. 103-118.

  26. G. Chen and M. Smith, “Global instruction scheduling on the machine SUIF,” in: Workshop on Interaction between Compilers and Computer Architecture, High Performance Computer Architecture 3 (February 1997).

  27. R. Stallman, Using and Porting the GNU Compiler Collection, http://gcc.gnu.org/onlinedocs/gcc_toc.html.

  28. P. Marwedel, “Tree-based mapping of algorithms to predefined structures,” in: Proc. Intern. Conf. on Computer-Aided Design (November 1995) (1995), pp. 586-593.

  29. G. Hadjiyiannis, S. Hanono, and S. Devadas, “ISDL: An instruction set description language for retargetability,” in: Proc. 34th Design Automat. Conf. (June 1997) (1997), pp. 299-302.

  30. D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 2nd Edition, New York (1998).

  31. M. S. Dolinskii, I. M. Zigel'man, and S. L. Belotskii, “An adjustable interpretive debugger of assembler programs,” Programmirovanie, No. 6, 36-45 (1995).

  32. A. Yu. Doroshenko and D. V. Kuivashev, “Intellectualization of vectorizing compilers for microprocessors with a long instruction word,” Probl. Progr., Nos. 1-2, 138-151 (2001).

  33. V. A. Evstigneev, Using Graph Theory in Programming [in Russian], A. P. Yershov (ed.), Nauka, Moscow (1985).

    Google Scholar 

  34. P. Briggs, “Register allocation via graph coloring,” Ph. D thesis, Rice University, Houston, Texas (April 1992) (1992).

    Google Scholar 

  35. Yu. A. Frantsuzov, “Instruction flow scheduling with delayed register allocation,” Programmirovanie, No. 1, 58-66 (1991).

  36. A. P. Yershov, An Introduction to Theoretical Programming [in Russian], Nauka, Moscow (1977).

    Google Scholar 

  37. M. Poletto and V. Sarkar, “Linear scan register allocation”, ACM TOPLAS, 21, No. 5, 895-913 (1999).

    Google Scholar 

  38. G. I. Shpakovskii, “A Method of scheduling traces and the architecture of a computer with a very long instruction,” ZRE, No. 11, 10-27 (1991).

  39. K. Ebcioglu and T. Nakatani, “A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture,” in: D. Gelerntner (ed.), Languages and Compilers for Parallel Computers, MIT Press, Cambridge, MA (1990), pp. 213-229.

    Google Scholar 

  40. B. Case, “Phillips hope to displace DSPs with VLIW,” Microprocessor Report, 8, No. 16, 12-15 (1994).

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Authors and Affiliations

  1. Institute of Program Systems of NANU, Kiev, Ukraine

    A. E. Doroshenko & D. V. Ragozin

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  1. A. E. Doroshenko
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  2. D. V. Ragozin
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Doroshenko, A.E., Ragozin, D.V. Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures. Cybernetics and Systems Analysis 39, 192–211 (2003). https://doi.org/10.1023/A:1024735105533

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