Stress characterization of device layers and the underlying Si_1−x Ge _x virtual substrate with high-resolution micro-Raman spectroscopy

Abstract

Silicon–germanium (Si–Ge) epitaxially grown mismatched heterostructures are becoming increasingly important for high-frequency microelectronics applications. One option under serious consideration is that of using Si–Ge virtual substrates, i.e., compositionally graded layers designed to accommodate the lattice mismatch between the underlying Si substrate and the overlying active epilayers(s). This assists in the prevention of misfit dislocations that can impact adversely on the active device regions. The stress in both device silicon cap layers and the underlying Si_1−x Ge _x virtual substrates is characterized with high-resolution micro-Raman spectroscopy (μRS). The device layers of the samples studied composed of a 7-nm thick silicon channel, a 6-nm thick SiGe layer and were capped with a 7-nm thick silicon layer. The device layers are grown over a 1-μm thick constant composition Si_0.70Ge_0.30 virtual substrate capping layer, and the Si-Ge virtual substrate is grown on a p⁺-type (0 0 1) silicon wafer with a thickness of about 500 μm. μRS measurement results with a 488-nm Ar⁺ visible laser source indicate that the Si_0.70Ge_0.30 capping layer at the virtual substrate is fully unstrained, while the top silicon cap layer is in extremely high tension. The use of a 325-nm HeCd UV laser for the μRS measurements, which probes only a very small depth into the Si cap layer (approximately 9 nm) confirms this high tensile stress is in the top silicon cap layer. The tensile stress in the top silicon cap layer is estimated to be as large as 2.4 GPa by analyzing the shift of the Si Raman peak with respect to the standard strain-free silicon sample. The measured stress value is almost equal to the theoretically predicted tensile stress that should exist in the fully strained Si cap layer. This implies that the Si cap layer remains strained in samples with this structure.