Abstract
A novel algorithm and architecture for computing the optimal decision feedback equalizer (DFE) coefficients from a channel state information (CSI) estimate is present. The proposed algorithm maps well onto a linear chain of n highly pipelineable CORDIC based processing elements. It is thus well suited for VLSI implementation. Due to the very regular data flow, the number of processing elements may be reduced without sacrificing computational latency by recycling the data through a chain of less than n processing elements.
The proposed architecture computes the optimal DFE coefficients of a twelve tap symbol spaced DFE suitable for HIPERLAN I in 2.7 μs and requires only 0.7 mm2 area on a 0.35 μm CMOS process, assuming a clock frequency of 100 MHz.
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References
Radio Equipment and Systems (RES): 1995, ‘HIgh PERformance Radio Local Area Network (HIPERLAN), Type 1 functional specification’. Technical Report ETS 300 652, European Telecommunications Standards Institute (ETSI).
J.G. Proakis, “ Chapter 26: Channel Equalization,” in The Communications Handbook. J.D. Gibson (ed.), 1997, pp. 339–363.
C.E. Belfiore and J.H. Park, Jr., “ Decision Feedback Equalization,” in Proceedings of the IEEE vol. 67, no. 8, 1979, pp. 1143–1156.
R.W. Lucky, J. Salz, and E.J. Weldon, Jr., Principles of Data Communication, Ch. 6: Equalization of the Baseband System, 1969, pp. 128–165. McGraw-Hill.
G. David Forney, Jr., “ Maximum-Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference,” IEEE Transactions on Information Theory, vol. IT-18, no. 3, 1972, pp. 363–378.
S.A. Fechtel, H. Meyr, and M. Moenenclay, Digital Communication Receivers: Synchronization, Channel Estimation, andSignal Processing, Wiley Series in Telecommunications and Signal Processing. Wiley, 1998.
S.A. Fechtel and H. Meyr, “ Optimal Parametric Feedforward Estimation of Frequency-Selective Fading Radio Channels,” IEEE Transactions on Communications, vol. 42, no. 2/3/4, 1994, pp. 1639–1650.
N. Al-Dhahir and J.M. Cioffi, “ MMSE Decision-Feedback Equalizers: Finite-Length Results,” IEEE Transactions on Information Theory, vol. 41, no. 4, 1995, pp. 961–975.
N. Al-Dhahir and A.H. Sayed, “ CORDIC-Based MMSE-DFE Coefficient Computation,” Digital Signal Processing, vol. 9, 1999, pp. 178–194.
A. Liavas and S. Theodoridis, “ Efficient Levinson-and Schurtype algorithms for block near-to-Toeplitz systems of equations,” Signal Processing, vol. 35, 1994, pp. 241–255.
T. Kailath and A.H. Sayed, “ Displacement Structure: Theory and Applications,” SIAM Review, vol. 37, no. 3, 1995, pp. 297–386.
J. Aldis, “ Equalisation method, Particularly for Offset Modulation Types,” European Patent EP0998083, 2000.
J.G. Proakis, Digital Communications. McGraw-Hill, 1995.
S.A. Fechtel and H. Meyr, “ An Investigation of Channel Equalization Techniques for Moderately Rapid Fading HF-Channels,” in International Conference on Communications (ICC), vol. 2, 1991, pp. 768–772.
T. Sailer, “ Decision Feedback Equalization for Powerline and HIPERLAN,” Ph.D. thesis, Electronics Lab, Swiss Federal Institute of Technology, ETH Z¨urich, 2001.
T. Kailath and J. Chun, “ Generalized Displacement Structure for Block-Toeplitz, Toeplitz-Block, and Toeplitz-Derived Matrices,” SIAM Journal on Matrix Analysis and Applied Mathematics, vol. 15, no. 1, 1994, pp. 114–128.
G.H. Golub and C.F.V. Loan, Matrix Computations, Johns Hopkins Series in the Mathematical Sciences. Johns Hopkins University Press, 1996.
I. Schur, “ ¨ Uber Potenzreihen, die im Inneren des Einheitskreises beschr¨ankt sind,” Journal f¨ur Reine und Angewandte Mathematik, vol. 147, 1917, pp. 205–232.
O. Axelsson, Iterative Solution Methods. Cambridge University Press, 1994.
J.E. Volder, “ The CORDIC Trigonometric Computing Technique,” IRE Transactions on Electronic Computers, vol. EC-8, 1959, pp. 330–334.
J.S. Walther, “ An Unified Algorithm for Elementary Functions,” in Proceedings Spring Joint Computer Conference, vol. 38, 1971, p. 397.
N. Benvenuto, P. Bisaglia, A. Salloum, and L. Tomba, “ Worst Case Equalizer for Noncoherent HIPERLAN Receivers,” IEEE Transactions on Communications, vol. 48, no. 1, 2000, pp. 28–36.
AMS Austria Mikro Systeme International AG, “ 0. 35 Micron Standard Cell 3.3V Databook-0.35 µm CMOS Digital Core Cells 3.3 V,” 2000, http://asic.amsint.com/databooks/csx33/core/.
Texas Instruments, “ TMS320C6201 Fixed-Point Digital Signal Processor (SPRS051G),” 2000. http://www-s.ti.com/sc/ psheets/sprs051g/sprs051g.pdf.
Semiconductor Insights, “ A Quick Look Analysis of the Texas Instruments TMS320C6201 BGJL DSP,” http://www.semiconductor.com/reports/asp/ShowSummary.asp?KeyColumn=218.
Texas Instruments, “TMS320C6000 Power Consumption Summary (SPRA486B),” 1999. http://www-s.ti.com:80/sc/psheets/spra486b/spra486b.pdf.
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Sailer, T., Tröster, G. An Efficient VLSI Architecture for Computing Decision Feedback Equalizer Coefficients from the Channel State Information. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 35, 91–103 (2003). https://doi.org/10.1023/A:1023340005481
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DOI: https://doi.org/10.1023/A:1023340005481