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High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations

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Abstract

The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform.

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Authors and Affiliations

  1. Dept. ETRO, Vrije Universiteit Brussel/IMEC, Pleinlaan 2, B-1050, Brussels, Belgium

    Y. Andreopoulos, P. Schelkens & J. Cornelis

  2. Inter-University Micro-Electronics Center—IMEC, Kapeldreef 75, B-3001, Leuven, Belgium

    G. Lafruit

  3. Development Programs Department, Intracom S.A., Athens, Greece

    K. Masselos

Authors
  1. Y. Andreopoulos
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  2. P. Schelkens
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  3. G. Lafruit
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  4. K. Masselos
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  5. J. Cornelis
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Andreopoulos, Y., Schelkens, P., Lafruit, G. et al. High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 34, 209–226 (2003). https://doi.org/10.1023/A:1023244201750

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  • DOI: https://doi.org/10.1023/A:1023244201750

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