Skip to main content
SpringerLink
Log in

An Efficient In-Place VLSI Architecture for Viterbi Algorithm

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

This paper presents a novel design of Viterbi decoder based on in-place state metric update and hybrid survivor path management. By exploiting the in-place computation feature of the Viterbi algorithm, the proposed design methodology can result in high-speed and modular architectures suitable for those Viterbi applications with large constraint length. This feature is not only applied to the design of highly regular ACS units, but also exploited in the design of trace-back units for the first time. The proposed hybrid survivor path management based on the combination of register-exchange and trace-back schemes cannot only reduce the number of memory operations, but also the size of memory required. Compared with the general hybrid trace-back structure, the overhead of register-exchange circuit in our architecture is significantly less. Therefore, the proposed architecture can find promising applications in digital communication systems where high-speed large state Viterbi decoders are desirable.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

eferences

  1. A.J. Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm," IEEE Transactions on Information Theory, vol. 13, 1967, pp. 260-269.

    Article  MATH  Google Scholar 

  2. S. Lin and D.J. Costello, Jr., Error Control Coding: Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall Inc., 1983.

  3. P.J. Black and T.H. Meng, "A 140-Mb/s, 32-State Radix-4 Viterbi Decoder," IEEE Journal of Solid-State Circuits, vol. 27, 1992, pp. 1877-1885.

    Article  Google Scholar 

  4. A.K. Yeung and J.M. Rabaey, "A 210-Mb/s Radix-4 Bit-Level Pipelined Viterbi Decoder," ISSCC Digest of Technical Papers, 1995, pp. 88-89.

  5. S. Ranpara and S.H. Dong, "A low-Power Viterbi Decoder Design for Wireless Communications Applications," in Proc. of IEEE Int. Conf. ASIC/SOC, 1999, pp. 377-381.

  6. T. Kamada et al., "A an Area Effective Standard Cell Based Channel Decoder LSI for Digital Satellite TV Broadcasting," VLSI Signal Processing, vol. IX, 1996, pp. 337-346.

    Article  Google Scholar 

  7. X.-Y. Hu, C.-M. Zhao, and X.-H. Yu, "ARobustViterbi Decoder and its Application to Terrestrial HDTV Broadcasting," IEEE Transactions on Broadcasting, vol. 43, no. 2, 1997, pp. 227-234.

    Article  Google Scholar 

  8. K. Mueller et al., "A Low-Cost DVB Compliant Viterbi and Reed-Solomon Decoder," IEEE Transactions on Consumer Electronics, vol. 43, 1997, pp. 448-452.

    Article  Google Scholar 

  9. M.-D. Shieh et al., "Design and Implementation of a DAB Channel Decoder," IEEE Transactions on Consumer Electronics, vol. 45, 1999, pp. 553-562.

    Article  Google Scholar 

  10. H.-L. Hou, "Implementing the Viterbi Algorithm," IEEE Signal Processing Magzine, vol. 12, 1995, pp. 42-52.

    Article  Google Scholar 

  11. J. Sparso, H.N. Jorgensen, E. Paaske, S. Pedersen, and T. Rubner-Petersen, "An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, 1991, pp. 90-97.

    Article  Google Scholar 

  12. I. Kang and A.N. Willson, Jr., "Low-Power Viterbi Decoder for CDMA Mobile Terminals," IEEE Journal of Solid-State Circuits, vol. 33, 1998, pp. 473-482.

    Article  Google Scholar 

  13. Y.-N. Chang, H. Suzuki, and K.K. Parhi, "A 2-Mb/s 256-State 10-mW Rate-1/3 Viterbi Decoder," IEEE Journal of Solid-State Circuits, vol. 35, 2000, pp. 826-834.

    Article  Google Scholar 

  14. M.-B. Lin, "New Path History Management Circuits for Viterbi Decoders," IEEE Transactions on Communications, vol. 48, no. 10, 2000, pp. 1605-1608.

    Article  Google Scholar 

  15. B. Cypher and C.B. Shung, "Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm," IEEE Journal of VLSI Signal Processing, vol. 5, 1993, pp. 85-94.

    Article  MATH  Google Scholar 

  16. T.K. Throng, M.-T. Shih, I.S. Reed, and E.H. Satorius, "A VLSI Design for a Trace-Back Viterbi Decoder," IEEE Transactions on Communications, vol. 40, no. 3, 1992, pp. 616-624. 324 Chang

    Article  Google Scholar 

  17. P.J. Black and T.H.-Y. Meng, "A Unified Approach to the Viterbi Algorithm State Metric Update for Shift Register Processes," IEEE ICASSP, vol. 5, 1992, pp. 629-632.

    Google Scholar 

  18. M. Biver, H. Kaeslin, and C. Tommasini, "In-Place Updating of Path Metrics in Viterbi Decoders," IEEE Journal of Solid-State Circuits, vol. 24, 1989, pp. 1158-1160.

    Article  Google Scholar 

  19. L.R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Englewood Cliffs, NJ: Prentice-Hall Inc., 1975.

  20. C.B. Shung et al., "VLSI Architectures for Metric Normalization in the Viterbi Algorithm," IEEE International Conference on Communications, vol. 4, 1990, pp. 1726-1728.

    Google Scholar 

  21. J.A. Ryu et al., "ANewLowPowerViterbi Decoder Architecture with Glitch Reduction," IEEE Asia Pacific Conference on ASIC, 1999, pp. 83-86.

  22. P.J. Black and T.H.-Y. Meng, "Hybrid Survivor Path Architectures for Viterbi Decoders," International Conference on Acoustics, Speech, and Signal Processing, vol. 1, 1993, pp. 433-436.

    Google Scholar 

  23. E. Boutillon and N. Demassieux, "High Speed Low Power Architecture for Memory Management in a Viterbi Decoder," in Proc. IEEE International Symposium on Circuits and Systems, 1996, vol. 4, pp. 284-287.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan

    Yun-Nan Chang

Authors
  1. Yun-Nan Chang
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chang, YN. An Efficient In-Place VLSI Architecture for Viterbi Algorithm. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 317–324 (2003). https://doi.org/10.1023/A:1022246815354

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1023/A:1022246815354

Search

Navigation