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An Efficient IDCT Processor Design for HDTV Applications

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Abstract

This paper proposes a high performance and low cost inverse discrete cosine transform (IDCT) processor for high definition Television (HDTV) applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate the one-dimensional (1-D) IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multiplier that implements multiplication with IDCT coefficients are first scaled and optimized by using the common sub-expression techniques. Based on these techniques, the data-path in the proposed two-dimensional (2-D) IDCT design costs 7504 gates plus 1024 bits of memory with 100 M pixels/sec throughput according to the cost estimation based on the cell library of COMPASS 0.6 μm SPDM CMOS technology. Also, we have verified that the precision analysis of the proposed 2-D 8 × 8 IDCT meets the demands of IEEE Std. 1180-1990. Due to the good performance in the computing speed as well as the hardware cost, the proposed design is compact and suitable for HDTV applications. This design methodology can be applied to forward DCT as well as other transforms like discrete sine transform (DST), discrete Fourier transform (DFT), and discrete Hartley transform (DHT).

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References

  1. K.R. Rao and J.J. Hwang, Techniques and Standards for Image, Video and Audio Coding, New Jersey: Prentice Hall, 1996.

    Google Scholar 

  2. N. Ahmed, T. Natarajan, and K.R. Rao, “Discrete Cosine Transform,” IEEE Trans.Communications, vol. COM-23, 1974, pp. 90–93.

    MathSciNet  Google Scholar 

  3. A.K. Jain, Fundamentals of Digital Image Processing, Englewood Cliffs, NJ 07632: Prentice-Hall, 1989.

  4. R.J. Clark, “Relation §etween the Karhunen-Loeve and Cosine Transform,” Proc.of IEE, vol. 128, pt. F, no. 6, 1981, pp. 359–360.

    Google Scholar 

  5. A. Rosenfeld and A.C. Kak, Digital Picture Processing, 2nd ed. New York: Academic, 1982.

    Google Scholar 

  6. P. Pirsch, N. Demassieux, and W. Gehrke, “VLSI Architectures for Video Compression-A Survey,” Proceedings of the IEEE, vol. 83, no. 2, 1995, pp. 220–246.

    Article  Google Scholar 

  7. P. Duhamel, C. Guillemot, and J.C. Carlach, “ADCTChip Based on a New Structured and Computationally Efficient DCT Algo-rithm,” in ISCAS'90, May 1990, Issy-les-Moulineaux, France, pp. 77–80.

  8. C.W. Kok, “Fast Algorithm for Computing Discrete Cosine Transform,” IEEE Trans.on SP, vol. 45, no. 3, 1997, pp. 757–760.

    Article  Google Scholar 

  9. M. Vetterli and A. Ligten§erg, “ADiscrete Fourier-Cosine Transform Chip,” IEEE Journal on SAC., vol. SAC-4, no. 1, 1986, pp. 49–61.

    Google Scholar 

  10. K.W. Current and J.R. Parkhurst, “Unified Forward and Inverse Discrete Cosine Transform Architecture and Proposed VLSI Implementation,” Int.J.Electronics, vol. 69, no. 2, 1990, pp. 233–246.

    Article  Google Scholar 

  11. H.S. Hou, “A Fast Recursive Algorithm for Computing the Discrete Cosine Transform,” IEEE Trans.on Acoustics, Speech, and Signal Processing, vol. ASSP-35, no. 10, 1987, pp. 1455–1461.

    Google Scholar 

  12. Z. Cvetkovic and M.V. Popovic, “New Fast Recursive Algorithms for the Computation of the Discrete Cosine and Sine Transforms,” IEEE Trans.on Signal Processing, vol. 40, no. 8, 1992, pp. 2083–2086.

    Article  MATH  Google Scholar 

  13. C. Loeffler, A. Ligten§erg, and G.S. Moschytz, “Practical Fast 1D DCT Algorithms with 11 Multiplications,” in Proc.ICASSP 1989, vol. 2, 1989, pp. 988–991.

    Google Scholar 

  14. C. Chakra§arti and J. JaJa, “Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition,” IEEE Trans.on Computers, vol. 39, no. 11, 1990, pp. 1359–1368.

    Article  Google Scholar 

  15. N.I. Cho and S.U. Lee, “DCT Algorithms for VLSI Parallel Implementation,” IEEE Trans.on ASSP., vol. 38, no. 1, 1990, pp. 121–127.

    Google Scholar 

  16. L.W. Chang and M.C. Wu, “AUnified Systolic Array for Discrete Cosine and Sine Transforms,” IEEE Trans.on SP, vol. 39, no. 1, 1991, pp. 192–194.

    Article  MathSciNet  Google Scholar 

  17. Y.H. Chan and W.C. Siu, “A Cyclic Correlated Structure for the Realization of Discrete Cosine Transform,” IEEE Trans.on CAS-II, vol. 39, no. 21, 1992, pp. 109–113.

    MATH  Google Scholar 

  18. J.I. Guo, C.M. Liu, and C.W. Jen, “A New Array Architecture for Prime Length Discrete Cosine Transform,” IEEE Trans.on SP, vol. 41, no. 1, 1993, pp. 436–442.

    Article  MATH  Google Scholar 

  19. M.T. Sun, T.C. Chen, and A.M. Gottlie§, “VLSI Implementation of a 16 x 16 Discrete Cosine Transform,” IEEE Trans.on CAS, vol. 36, no. 4, 1989, pp. 610–616.

    Article  Google Scholar 

  20. T.C. Chen, M.T. Sun, and A.M. Gottlie§, “VLSI Implementation of a 16 x 16 DCT,” in Proc.ICASSP 1988, vol. 4, 1988, pp. 1973–1976.

    Google Scholar 

  21. Y.H. Chan and W.C. Siu, “On the Realization of Discrete Cosine Transform Using the Distri§uted Arithmetic,” IEEE Trans.on CAS-I, vol. 39, no. 9, 1992, pp. 705–712.

    Article  MATH  Google Scholar 

  22. A. Madisetti and A.N. Wilson, Jr., “A 100 MHZ 2-D 8 x 8 DCT/IDCT Processor for HDTV Applications,” IEEE Trans.on Video Technology, vol. 5, no. 2, 1995, pp. 158–164.

    Article  Google Scholar 

  23. D. Slawecki and W. Li, “DCT/IDCT Processor Design for High Data Rate Image Coding,” IEEE Trans.on CSVT, vol. 2, no. 2, 1992, pp. 135–146.

    Google Scholar 

  24. J.I. Guo, C.M. Liu, and C.W. Jen, “The Efficient Memory-Based VLSI Arrays for DFT and DCT,” IEEE Trans.on CAS-II, vol. 39, no. 10, 1992, pp. 723–733.

    MATH  Google Scholar 

  25. G.K. Ma and F.J. Taylor, “Multiplier Policies for Digital Signal Processing,” IEEE ASSP Magazine, vol. 7, no. 1, 1990, pp. 6–20.

    Article  Google Scholar 

  26. D.R. Bull and D.H. Horrocks, “Primitive Operator Digital Filters,” IEE Proc.Circuits Devices Syst., vol. 138, no. 3, 1991, pp. 401–412.

    Article  Google Scholar 

  27. A.G. Dempster and M.D. Macleod, “Constant Integer Multi-plication Using Minimum Adders,” IEE Proc.Circuits Devices Syst., vol. 141, no. 5, 1991.

  28. A.G. Dempster and M.D. Macleod, “Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters,” IEEE Trans.Circuits Sys., vol. 42, no. 9, 1995, pp. 569–577.

    Article  MATH  Google Scholar 

  29. R.I. Hartley, “Su§expression Sharing in Filters Using Canonic Signed Digit Multipliers,” IEEE Trans.Circuits Sys., vol. 43, no. 2, 1996, pp. 677–688.

    Article  Google Scholar 

  30. M. Potkonjak, M. Srivastava, and A.P. Chandrakasan, “Multi-ple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Su§expression Elimination,” IEEE Trans.Computer-Aided Design., vol. 15, no. 2, 1996, pp. 151–165.

    Article  Google Scholar 

  31. Compass, PASSPORT li§rary, 0.6 micron 5-volt high performance standard cell li§rary, 1996.

  32. IEEE std 1180–1990, “IEEE Standard Specifications for the Implementations of 8 x 8 Inverse Discrete Cosine Transform,” Dec. 6, 1990.

  33. C.-Y. Hung and P. Landman, “Compact Inverse Discrete Cosine Transform Circuit for MPEG Video Decoding,” IEEE Workshop on Signal Processing Systems, 1997, pp. 364–373.

  34. T.H. Chen, “A Cost Effective 8 ×8 2-D IDCT Core Processor with Folded Architecture,” IEEE Trans.on Consumer Electronics, vol. 45, no. 2, 1999, pp. 333–339.

    Article  Google Scholar 

  35. J. Hunter and J.V. McCanny, “Discrete Cosine Transform Generator for VLSI Synthesis,” in Proc.ICASSP, vol. 5, 1998, pp. 2997–3000.

    Google Scholar 

  36. R. Ram§aldi, A. Uguzzoni, and R. Guerrieri, “A 35 μ W 1.1 V Gate Array 8 x 8 IDCT for Video Technology,” in Proc.ICASSP, vol. 5, 1998, pp. 2993–2996.

    Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, 621, Taiwan, Republic of China

    Jiun-In Guo

  2. Department of Electronics Engineering, National Lien-Ho Institute of Technology, Miaoli, 360, Taiwan, Republic of China

    Jui-Cheng Yen

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  1. Jiun-In Guo
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  2. Jui-Cheng Yen
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Guo, JI., Yen, JC. An Efficient IDCT Processor Design for HDTV Applications. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 33, 147–155 (2003). https://doi.org/10.1023/A:1021154120916

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