A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems


In this paper, we propose a system-level design methodology for the efficient exploration of the architectural parameters of the memory sub-systems, from the energy-delay joint perspective. The aim is to find the best configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space. The target system architecture includes the processor, separated instruction and data caches, the main memory, and the system buses. To achieve a fast convergence toward the near-optimal configuration, the proposed methodology adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of the memory sub-system architecture. The exploration strategy is based on the Energy-Delay Product (EDP) metric taking into consideration both performance and energy constraints. The effectiveness of the proposed methodology has been demonstrated through the design space exploration of a real-world case study: the optimization of the memory hierarchy of a MicroSPARC2-based system executing the set of Mediabench benchmarks for multimedia applications. Experimental results have shown an optimization speedup of 2 orders of magnitude with respect to the full search approach, while the near-optimal system-level configuration is characterized by a distance from the optimal full search configuration in the range of 2%.

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  1. 1.

    Bahar, R. I., G. Albera, and S. Manne. Power and Performance Tradeoffs Using Various Caching Strategies. In ISLPED-98: ACM/IEEE Int. Symposium on Low Power Electronics and Design, Monterey, CA.

  2. 2.

    Bellas, N., I. N. Hajj, D. Polychronopoulos, and G. Stamoulis. Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems, vol. 8, no.3, 2000.

  3. 3.

    Benini, L., A. Macii, E. Macii, and M. Poncino. Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. Design and Test of Computers, vol. 17, no.2, pp. 74–85, 2000.

    Google Scholar 

  4. 4.

    Brockmeyer, E., L. Nachtergaele, F. Catthoor, J. Bormans, and H. D. Man. Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multi Media Processor. IEEE Trans. on Multi-Media, vol. 1, no.2, pp. 202–216, 1999.

    Google Scholar 

  5. 5.

    Brooks, D., V. Tiwari, and M. Martonosi.Wattch:A Framework for Architectural-Level Power Analysis and Optimizations. In ISCA 2000: 2000 International Symposium on Computer Architecture.Vancouver BC, Canada, pp. 83–94, 2000.

  6. 6.

    Catthoor, F., S.W.E.D. Greef, F. Franssen, L. Nachtergaele, and H.D. Man. System-Level Transformations for Low Power Data Transfer and Storage. In: R.B.A. Chandrakasan (ed.): Low Power CMOS Design. IEEE Press, 1998a, pp. 609–618.

  7. 7.

    Catthoor, F., S. Wuytack, E.-D. Greef, F. Balasa, and P. Slock. System Exploration for Custom Low Power Data Storage and Transfer. New York: Marcel Dekker, Inc., 1998b.

    Google Scholar 

  8. 8.

    Cmelik, B. and D. Keppel. Shade: A Fast Instruction-Set Simulator for Execution Profiling. In ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, 1994.

  9. 9.

    Conte, T. M., K. N. Menezes, S. W. Sathaye, and M. C. Toburen. System-Level Power Consumption Modeling and Tradeoff Analysis Techniques for Superscalar Processor Design. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no.2, pp. 129–137, 2000.

    Google Scholar 

  10. 10.

    Danckaert, K., K. Masselos, F. Catthoor, H. D. Man, and C. Goutis. Strategy for Power Efficient Design of Parallel Systems. IEEE Trans. on VLSI Systems, vol. 7, no.2, pp. 258–265, 1999.

    Google Scholar 

  11. 11.

    W. Fornaciari, M. Polentarutti, D. Sciuto, and C. Silvano. Power Optimization of System-Level Address Buses based on Software Profiling. In CODES-2000: 8th Int. Workshop on Hardware/Software Co-Design. San Diego, CA, 2000.

  12. 12.

    Fornaciari, W., D. Sciuto, C. Silvano, and V. Zaccaria. A Design Framework to Efficiently Explore Energy-Delay Tradeoffs. In: Proceedings of CODES-2001: Ninth International Symposium on Hardware/Software Codesign. 2001b, pp. 260–265.

  13. 13.

    Fornaciari, W., D. Sciuto, C. Silvano, and V. Zaccaria. Fast System-Level Exploration of Memory Architecures Driven by Energy-Delay Metrics. In Proceedings of ISCAS-2001: International Symposium on Circuits and Systems, vol. IV, 2001a, pp. 502–506.

    Google Scholar 

  14. 14.

    Givargis, T. D., F. Vahid, and J. Henkel. Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-ChipDesigns. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems, vol. 9, no.4, 2001a.

  15. 15.

    Givargis, T. D., F. Vahid, and J. Henkel.System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. ICCAD 2001, pp. 25–30, 2001b.

  16. 16.

    Gonzales, R., and M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid-State Circuits, vol. 31, no.9, pp. 1277–1284, 1996.

    Google Scholar 

  17. 17.

    P. Hicks, M. Walnock, and R. M. Owens. Analysis of Power Consumption in Memory Hierarchies. In ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design. Monterey, CA, 1997, pp. 239–242.

  18. 18.

    Kamble, M. B. and K. Ghose. Analytical Energy Dissipation Models for Low Power Caches. In ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design, 1997.

  19. 19.

    Keutzer, K., S. Malik, A. R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System Level Design: Orthogonolization of Concerns and Platform-Based Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no.172, 2000.

  20. 20.

    J. K. Kin, M. Gupta, and W. H. Mangione-Smith. Filtering Memory References to Increase Energy Efficiency. IEEE Trans. on Computers, vol. 49, no.1, 2000.

    Google Scholar 

  21. 21.

    Lee, C., M. Potkonjak, and W. H. Mangione-Smith. MediaBench: ATool for Evaluating Multimedia and Communication Systems. In Micro 30, 1997a.

  22. 22.

    Lee, T., V. Tiwari, and S. Malik.1997b, “Power analysis and minimization techniques for embedded DSP software,” 1997b.

  23. 23.

    Y. Li, and J. Henkel. A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems. In DAC-35: ACM/IEEE Design Automation Conference, 1998.

  24. 24.

    NEC: 16M-bit Synchronous DRAM Data Sheet, Doc. No. M12939EJ3V0DS00, 1998.”

  25. 25.

    Panda, P., and N. Dutt. Low-Power Memory Mapping Through Reducing Address Bus Activity. IEEE Trans. on VLSI Systems. vol. 7, no.3, pp. 309–320, 1999.

    Google Scholar 

  26. 26.

    Russell, J., and M. Jacome. Software Power Estimation and Optimization for High Performance, 32–bit Embedded Processors. In International Conference on Computer Design: VLSI in Computers and Processors. pp. 328–333, 1998.

  27. 27.

    Sami, M., D. Sciuto, C. Silvano, and V. Zaccaria. Power Exploration for Embedded V LIWArchitectures. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD-2000). IEEE Computer Society Press. Los Alamitos, California, 2000, pp. 498–503.

    Google Scholar 

  28. 28.

    Shiue, W.-T., and C. Chakrabarti. Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. In DA C99: Design Automation Conference. New Orleans, LA, 1999.

  29. 29.

    C. L. Su, and A.M. Despain. Cache Design Trade-offs for Power and Performance Optimization: A Case Study. In ISLPED-95: ACM/IEEE Int. Symposium on Low Power Electronics and Design, 1995.

  30. 30.

    Udayanarayanan, S., and C. Chakrabarti. Energy-Efficient Code Generation for DSP56000 Family. In Proceedings of the 2000 International Symposium on Low Power Electronics and Design (ISLPED-00). ACM Press, N.Y., 2000, pp. 247–249.

    Google Scholar 

  31. 31.

    N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye. Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower. In ISCA 2000: 2000 International Symposium on Computer Architecture.Vancouver BC, Canada, 2000.

  32. 32.

    Wilton, S. E., and N. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches.Technical Report 93/5, Digital Equipment CorporationWestern Research Lab, 1994.

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Fornaciari, W., Sciuto, D., Silvano, C. et al. A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems. Design Automation for Embedded Systems 7, 7–33 (2002). https://doi.org/10.1023/A:1019791213967

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  • Design space exploration
  • power and performance optimization