Abstract
A new intermediate representation for software pipelined loops with conditions is proposed in the paper. The representation allows separation of operations from different paths and their conditional, as well as speculative scheduling, including speculative computation of conditions. An algorithm that transforms the representation into the executable code is presented. The algorithm uses the notion of finite automata to represent the execution of separate paths as threads of control that are canceled or approved by operations that actually compute the conditions. The approach may be used in conjunction with different scheduling techniques to reconstruct the control flow graph from the final schedule directly. It inherently solves the problems of overlapped predicate lifetimes and speculation. The approach provides also a novel formal model for loop execution.
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REFERENCES
K. Ebcioglu, A Compilation Technique for Software Pipelining of Loops with Conditional Jumps, Proc. 20th Ann. Workshop on Microprogramming, (MICRO-20), pp. 69–79 (1987).
S.-M. Moon and K. Ebcioglu, An Efficient Resource-Constrained Global Scheduling Technique for Superscalar and VLIW Processors, Proc. 25th Ann. Int'l. Symp. Microarch, (MICRO-25), pp. 55–71 (1992).
A. Nikolau, Percolation Scheduling: A Parallel Compilation Technique, TR-85-678, Cornell University, (1985).
J. Ferrante, K. J. Ottenstein, and J. D. Warren, The Program Dependence Graph and its Use in Optimization, ACM Trans. Prog. Lang. Syst., 9: 310–349 (1987).
N. J. Warter, S. A. Mahlke, W-M. W. Hwu, and B. R. Rau, Reverse If-Conversion, Proc. ACM SIGPLAN Conf. Prog. Lang. Design and Implementation, pp. 290–299 (1993).
B. R. Rau, Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops, Proc. 27th Ann. Int'l. Symp. Microarch, (MICRO-27), pp. 63–74 (1994).
M. Stoodley and C. Lee, Software Pipelining Loops with Conditional Branches, Proc. 29th Ann. Int'l. Symp. Microarch, (MICRO-29) (1996).
B. Su and J. Wang, GURPR: A New Global Software Pipelining Algorithm, Proc. 24th Ann. Workshop Microprog. and Microarch, (MICRO-24), pp. 212–216 (1991).
Z. Tang, G. Chen, C. Zhang, Y. Zhang, B. Su, and S. Habib, GPMB-Software Pipelining Branch-Intensive Loops, Proc. 26th Ann. Int'l. Symp. Microarch, (MICRO-26) (1993).
N. J. Warter, J. W. Bockhaus, G. E. Haab, and K. Subramanian, Enhanced Modulo Scheduling for Loops with Conditional Branches, Proc. 25th Ann. Int'l. Symp. Microarch., (MICRO-25), pp. 170–179 (1992).
N. J. Warter-Perez and N. Partamian, Modulo Scheduling with Multiple Initiation Intervals, Proc. 28th Ann. Int'l. Symp. Microarch, (MICRO-28), pp. 111–118 (1995).
S. Shim and S.-M. Moon, Split-Path Enhanced Pipeline Scheduling for Loops with Control Flows, Proc. 31st Ann. Int'l. Symp. Microarch, (MICRO-31) (1998).
J. R. Allen, K. Kennedy, C. Porterfield, and J. Warren, Conversion of Control Dependence to Data Dependence, Proc. 10th ACM Symp. Principles of Prog. Lang., pp. 177–189 (1983).
B. R. Rau, M. S. Schlansker, and P. P. Tirumalai, Code Generation Schema for Modulo Scheduled Loops, Proc. 25th Ann. Int'l. Symp. Microarch, (MICRO-25), pp. 158–69 (1992).
A. Aiken and A. Nicolau, Optimal Loop Parallelization, Proc. ACM SIGPLAN 1988 Conf. Prog. Lang. Design and Implementation, pp. 308–317 (1988).
D. Milicev and Z. Jovanovic, A Formal Model of Software Pipelining Loops with Conditions, Proc. 11th Int'l. Parallel Processing Symp, (IPPS '97), pp. 554–558 (1997).
D. Milicev and Z. Jovanovic, Predicated Software Pipelining Technique for Loops with Conditions, Proc. 12th Int'l. Parallel Processing Symp, (IPPS '98) (1998).
A. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques, and Tools, Addison-Wesley (1986).
D. Milicev and Z. Jovanovic, Code Generation for Software Pipelined Loops with Conditions, Technical Report TI-RTI-99-0041, University of Belgrade, Faculty of Electrical Engineering (1999). Also available at: http://www.rcub.bg.ac.yu/~dmilicev
U. Schwiegelshohn, F. Gasperoni, and K. Ebcioglu, On Optimal Parallelization of Arbitrary Loops, J. of Parallel and Distributed Computing, 11:130–134 (1991).
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Milicev, D., Jovanovic, Z. Control Flow Regeneration for Software Pipelined Loops with Conditions. International Journal of Parallel Programming 30, 149–179 (2002). https://doi.org/10.1023/A:1015453520790
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DOI: https://doi.org/10.1023/A:1015453520790