Abstract
This paper shows how a parallel prefix adder computing S = A + B may be slightly modified to yield a new adder structure, called a “flagged prefix adder”, capable of returning therelated computation pairs A + B and A + B + 1, or, if the bits of B are inverted, A − B and B − A. This adder is of use in digital communications applications and video compression, as well as arithmetic processor designs. The new adder uses 25% less transistors than the conditional-sum adder, which has been used previously in such situations.
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Burgess, N. The Flagged Prefix Adder and its Applications in Integer Arithmetic. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 31, 263–271 (2002). https://doi.org/10.1023/A:1015421507166
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DOI: https://doi.org/10.1023/A:1015421507166