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Extended Synchronous Dataflow for Efficient DSP System Prototyping

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Abstract

Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes it unsuitable for multimedia signal processing applications that need global states for efficient implementation. In this paper, we propose synchronous piggybacked dataflow (SPDF), an extension of SDF model to accommodate global states without side effects. Global states are accessed by a special block that piggybacks the global state update request on data samples. Such an extension enlarges the domain of application where dataflow representation can be used for rapid system prototyping. The only penalty it incurs is scheduling complexity since the scheduler now considers control dependency as well as data dependency. We present the static analysis of the SPDF model and an implementation technique for memory efficient code synthesis. Finally, we show experimental results with a real life example, MPEG-audio decoder, to present the novelty and usefulness of our approach.

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References

  1. Lee, E. A. and D. G. Messerschmitt. Synchronous Data Flow, Proceedings of the IEEE, vol. 75,no. 9, pp. 1235-1245, 1987.

    Google Scholar 

  2. Lauwereins, R., M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. GRAPE: A CASE Tool for Digital Signal Parallel Processing, IEEE ASSP Magazine, vol. 7,no. 2, pp. 32-43, April 1990.

    Google Scholar 

  3. Lee, E. A. and T. M. Parks. Dataflow Process Networks, Proceedings of the IEEE, vol. 83,no. 5, pp. 773-801, May 1995.

    Google Scholar 

  4. Synopsys Inc., COSSAP User Manual: VHDL Code Generation, 700 E. Middlefield Rd., Mountain View, CA 94043, USA.

  5. Buck, J., S. Ha, E. A. Lee, D. G. Messerschmitt. Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, International Journal of Computer Simulation, vol. 4, pp. 155-182, 1994.

    Google Scholar 

  6. Cadenee Design Systems, SPW User's Manual, 919 E. Hillsdale Blvd., Foster City, CA 94404, USA.

  7. Bhattacharya, B. and S. S. Bhattacharyya. Parameterized Dataflow Modeling of DSP Systems. In Proc. of International Conference on Acoustics, Speech, and Signal Processing, Istanbul, Turkey, June 2000.

  8. Ben-Romdhane, M., M. Vassiliou, L.-R. Dung. Rapid Prototyping of Multimedia Chip Sets. In Proc. of International Conference on Acoustics, Speech, and Signal Processing, 1999.

  9. Bhattacharyya, S. S., P. K. Murthy, and E. A. Lee. APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementation, Design Automation for Embedded Systems, vol. 2,no. 1, pp. 33-60, Jan. 1997.

    Google Scholar 

  10. Bhattacharyya, S. S., P. K. Murthy, and E. A. Lee. Synthesis of Embedded Software from Synchronous Dataflow Specifications, Journal of VLSI Signal Processing Systems, vol. 21,no. 2, June 1999.

  11. Murthy, P. K., S. S. Bhattacharyya, and E. A. Lee. Joint Minimization of Code and Data for Synchronous Dataflow Programs, Journal of Formal Methods in System Design, vol. 11,no. 1, pp. 41-70, July 1997.

    Google Scholar 

  12. Bhattacharyya, S. S., P. K. Murthy, and E. A. Lee. Optimized Software Synthesis for Synchronous Dataflow. In International Conference on Application Specific Systems, Architectures, and Processors, July 1997.

  13. Ade, M., R. Lauwereins, and J. A. Peperstraete. Implementing DSP Applications on Heterogeneous Targets Using Minimal Size Data Buffers. In Proc. IEEE International Workshop on Rapid System Prototyping, June 1996, pp. 166-172.

  14. Bhattacharyya, S. S. and E. A. Lee. Memory Management for Dataflow Programming of Multirate Signal Processing Algorithms, IEEE Trans. on Signal Processing, vol. 42,no. 5, May 1994.

  15. Sung, W., J. Kim, and S. Ha. Memory Efficient Software Synthesis from Dataflow Graph. In Proc. International Symposium on System Synthesis, Hsinchu, Taiwan, Dec. 1998.

  16. Nachtergaele, L., F. Catthoor, B. Kapoor, S. Janssens, and D. Moolenaar. Low Power Storage for H.263 Video Decoder. In Proc. IEEE International Workshop on VLSI Signal Processing, Monterey, CA, Oct. 1996, pp. 115-124.

  17. Brockmeyer, E., L. Nachtergaele, F. Catthoor, J. Bormans, and H. De Man. Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pell Motion Estimation on a Multimedia Processor, IEEE Transactions on Multimedia, vol. 1,no. 2, pp. 202-216, June 1999.

    Google Scholar 

  18. ISO/IEC International Standard IS 11172-3. Information Technology—Coding of Moving Pictures and Associated Audio for Digital Storage Media at Up to About 1.5Mbits/s.

  19. MPEG Digital Audio Coding, IEEE Signal Processing Magazine, pp. 59-81, Sept. 1997.

  20. Pino, J. L., T. M. Parks, and E. A. Lee. Mapping Multiple Independent Synchronous Dataflow Graphs onto Heterogeneous Multiprocessors. In Proc. of IEEE Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, CA, Oct. 31–Nov. 2, 1994.

  21. Bilsen, G., M. Engels, R. Lauwereins, and J. A. Peperstraete. Cyclo-Static Dataflow, IEEE Transactions on Signal Processing, vol. 44,no. 2, pp. 397-408, Feb. 1996.

    Google Scholar 

  22. Parks, T. M., J. L. Pino, and E. A. Lee. A Comparison of Synchronous and Cyclo-Static Dataflow. In Proc. IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, Oct. 29–Nov. 1, 1995.

  23. The Processing Graph Method Tool. In Proc. IEEE International Conference on Application Specific Systems, Architectures, and Processors, July 1997, pp. 263-271.

  24. Arvind, R. S. Nikhil, and K. K. Pingali. I-Structures: Data Structures for Parallel Computing. In Proc. of the Workshop on Graph Reduction, Santa Fe, NM, Sept. 28–Oct. 1, 1986.

  25. Sung, W. and S. Ha. Efficient and Flexible Cosimulation Environment for DSP Applications, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Issue on VLSI Design and CAD Algorithms, vol. E81-A,no. 12, pp. 2605-2611, Dec. 1998.

    Google Scholar 

  26. ARM Ltd., ARM Software Development Toolkit, http://www.arm.com/products/SDT.

  27. Visual C++ User's Guide. Microsoft Press, vol. 1.

  28. Oh, H. and S. Ha. Data Memory Minimization by Sharing Large Size Buffers. In Proc. Asia South Pacific Design Automation Conference, 2000.

  29. Ha, S. and E. A. Lee. Quasi-Static Scheduling for Multiprocessor DSP. In Proc. of IEEE International Symposium on Circuits and Systems, Singapore, June 1991.

  30. Cormen, T. H., C. E. Leiserson, R. L. Rivest. Introduction to Algorithms. The MIT Press.

  31. ISO/MPEG Working Groups, Fraunhofer Institute, and J. Hagman. Available at ftp://ftp.tnt.uni-hannover.de/pub/MPEG/audio/mpeg2/software/technical_report/dist08.tar.gz.

  32. Park, C., J. Jung, and S. Ha. Efficient Dataflow Representation of MPEG-1 Audio (Layer III) Decoder Algorithm with Controlled Global States. In Proc. IEEE Workshop on Signal Processing System: Design and Implementation, Taiwan, ROC, Oct. 1999.

  33. Park, C., J. Jung, and S. Ha. Extended Synchronous Dataflow for Efficient DSP System Prototyping. In Proc. IEEE International Workshop on Rapid System Prototyping, Florida, USA, June 1999.

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Park, C., Jung, J. & Ha, S. Extended Synchronous Dataflow for Efficient DSP System Prototyping. Design Automation for Embedded Systems 6, 295–322 (2002). https://doi.org/10.1023/A:1014070804761

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