Abstract
A question is considered as to the development of a procedure of testing combinational circuits with due regard for the power consumed during tests. It is shown that in the general case, the optimization problem of the consumable energy reduces to the known problem of discrete mathematics—the traveling salesman problem.
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REFERENCES
Nebel, W. and Mermet, J., Low Power Design in Deep Submicron Electronics, Boston: Kluwer, 1997.
Pedram, M., Power Minimization in IC Design: Principles and Applications, ACM Trans. Des. Autom. Electr. Syst., 1996, no. 1, pp. 3–56.
Zorian, Y., A Distributed BIST Control Scheme for Complex VLSI Devices, 11th IEEE VLSI Test Sympos., 1993.
Wang, S. and Gupta, S., ATPG for Heat Dissipation Minimization During Test Application, IEEE Trans. Comput., 1998, vol. 47, no. 2, pp. 256–262.
Corno, F., Prinetto, P., Rebaudengo, M., et al., A Test Pattern Generation Methodology for Low Power Consumption, IEEE Int. Test Conf., 1998.
Dabholkar, V. and Chkravarty, S., Two Techniques to Minimize Power Dissipation During Test Application in Scan Circuits, IEEE Asian Test. Conf., 1994.
Garey, M.L. and Johnson, D.S., Computers and Intractability: A Guide to the Theory of NPCompleteness, San Francisco: Freeman, 1979. Translation under the title Vychislitel'nye mashiny i trudnoreshaemye zadachi, Moscow: Mir, 1982.
Christofides, N., Graph Theory: An Algorithmic Approach, New York: Academic, 1975. Translated under the title Teoriya grafov. Algoritmicheskii podkhod, Moscow: Mir, 1978.
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Latypov, P.K. Energy Saving Testing of Circuits. Automation and Remote Control 62, 653–655 (2001). https://doi.org/10.1023/A:1010297931824
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DOI: https://doi.org/10.1023/A:1010297931824