System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

Abstract

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.

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Eles, P., Peng, Z., Kuchcinski, K. et al. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Design Automation for Embedded Systems 2, 5–32 (1997). https://doi.org/10.1023/A:1008857008151

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  • Hardware/software partitioning
  • co-synthesis
  • iterative improvement heuristics
  • simulated annealing
  • tabu search