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Efficient Verification of Parallel Real–Time Systems

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Abstract

This paper presents an efficient model checking algorithm for one–safe time Petri nets and a timed temporal logic. The approach is based on the idea of (1) using only differences of timing variables to be able to construct a finite representation of the set of all reachable states and (2) further reducing the size of this representation by exploiting the concurrency in the net. This reduction of the state space is possible, because the considered linear–time temporal logic is stuttering invariant. The firings of transitions are only partially ordered by causality and a given formula; therefore the order of firings of independent transitions is irrelevant, and only one of several equivalent interleavings has to be generated for the evaluation of the given formula. In this paper the theory of timing verification with time Petri nets and temporal logic is presented, a concrete model checking algorithm is developed and proved to be correct, and some experimental results demonstrating the efficiency of the method are given.

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Authors and Affiliations

  1. Department of Computer Science, Tokyo Institute of Technology, 2-12-1, O-okayama, Meguro, Tokyo, 152, Japan

    Tomohiro Yoneda

  2. Bremen Institute for Safe Systems, University of Bremen, Postfach 330 440, D - 28334, Bremen, Germany

    Bernd–Holger Schlingloff

Authors
  1. Tomohiro Yoneda
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  2. Bernd–Holger Schlingloff
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Yoneda, T., Schlingloff, B. Efficient Verification of Parallel Real–Time Systems. Formal Methods in System Design 11, 187–215 (1997). https://doi.org/10.1023/A:1008682131325

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