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Checking Combinational Equivalence of Speed-Independent Circuits

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Abstract

We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a “golden” hazard-free circuit C 1 and a “target” circuit C 2 that can be derived from C 1 through only combinational decomposition and extraction. Both circuits are assumed to be networks of single-output basic gates; multiple output gates such as arbiters, toggles, and dual-rail function blocks are not considered. We say that the circuits are combinationally equivalent if the decomposition and extraction preserves the essential functionality of the combinational blocks in the circuit and does not introduce hazards. The paper's focus is the bottleneck of the verification procedure, checking whether C 2 is hazard-free. We show that C 2 is hazard-free if and only if all of its signals are monotonic and acknowledged . We then show how cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are used to develop a verification technique for combinational equivalence that can be exponentially faster than applying traditional, more general verification techniques. This result can be useful for verifying logic synthesis and technology mapping procedures.

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References

  1. D. B. Armstrong, A. D. Friedman, and P. R. Menon. Design of asynchronous circuits assuming unbounded gate delays. IEEE Transactions on Computers, C-18(12):1110–1120, December 1969.

    Google Scholar 

  2. P. A. Beerel. CAD Tools for the Synthesis, Verification, and Testability of Robust Asynchronous Circuits. PhD thesis, Stanford University, August 1994.

  3. P. A. Beerel and T. H.-Y. Meng. Automatic gate-level synthesis of speed-independent circuits. In IEEE ICCAD Digest of Technical Papers, pages 581–586, 1992.

  4. P. A. Beerel and T. H.-Y. Meng. Semi-modularity and testability of speed-independent circuits. INTEGRATION, the VLSI journal, 13(3):301–322, September 1992.

    Google Scholar 

  5. P. A. Beerel and T. H.-Y. Meng. Logic transformations and observability don't cares in speed-independent circuits, 1993. In collection of papers of the ACM International Workshop on Timing Issues in the Specification of and Synthesis of Digital Systems.

  6. T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, Massachusetts Institute of Technology, 1987.

  7. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. In Proc. European Design and Test Conference, 1997.

  8. D. L. Dill. Trace theory for automatic hierarchical verification of speed-independent circuits. ACM Distinguished Dissertations, 1989.

  9. J. C. Ebergen. A verifier for network decompositions of command-based specifications. In Proc. of the 26th Annual HICSS, pages 310–318. IEEE Computer Society Press, 1993.

  10. G. Gopalakrishnan, E. Brunvand, N. Michell, and S. Nowick. A correctness criterion for asynchronous circuit validation and optimization. IEEE Transactions on Computer-Aided Design 13(11): 1309–1318, November 1994.

    Article  Google Scholar 

  11. M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. Analysis and identification of self-timed circuits. Formal Methods in System Design, 4(1):33–75, 1994.

    Google Scholar 

  12. A. Kondratyev, M. Kishinevsky, J. Cortadella, L. Lavagno, and A. Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, April 1997.

  13. A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. On the conditions for gate level speed-independence of asynchronous circuits, 1993. In collection of papers of the ACM International Workshop on Timing Issues in the Specification of and Synthesis of Digital Systems.

  14. A. Kondratyev, M. Kishinevsky, and A. Yakovlev. On hazard-free implementation of speed-independent circuits. In Proceedings of the Asian South Pacific Design Automation Conference, pages 241–248, 1995.

  15. K.-J. Lin and C.-S. Lin. Automatic synthesis of asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 296–301. IEEE Computer Society Press, 1991.

  16. J.-C. Madre and J.-P. Billon. Proving circuit correctness using formal comparison between expected and extracted behavior. In Proc. ACM/IEEE Design Automation Conference, pages 205–210, 1988.

  17. A. J. Martin. Programming in VLSI: from communicating processes to delay-insensitive VLSI circuits. In C.A.R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming. Addison-Wesley, 1990.

  18. K. McMillan. Trace theoretic verification of asynchornous circuits using unfoldings. In Proc. International Workshop on Computer Aided Verification n, pages 180–195, 1995.

  19. R. E. Miller. Switching Theory, Volume II: Sequential Circuits and Machines. Wiley, New York, 1965.

    Google Scholar 

  20. D. E. Muller and W. S. Bartky. A theory of asynchronous circuits. In Proceedings of an International Symposium on the Theory of Switching, pages 204–243. Harvard University Press, April 1959.

  21. O. Roig, J. Cortadella, and E. Pastor. Hierarchical gate-level verification of speed-independent circuits. In Asynchronous Design Methodologies pages 129–137. IEEE Computer Society Press, May 1995.

  22. O. Roig, J. Cortadella, and E. Pastor. Verification of asynchronous circuits by BDD-based model checking of petri nets. In 16th Intl. Conf. on Theory and Application of Petri-Nets, June 1995.

  23. S. H. Unger. Asynchronous Sequential Switching Circuits. New York:Wiley-Interscience, 1969. (re-issued by R. E. Krieger, Malabar, 1983).

    Google Scholar 

  24. K. van Berkel. Handshake Circuits: An Intermediary between Communicating Processes and VLSI. PhD thesis, Eindhoven University of Technology, 1992.

  25. V. I. Varshavky, editor. Self-Timed Control of Concurrent Processes. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990.

    Google Scholar 

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Authors
  1. Peter A. Beerel
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  2. Jerry R. Burch
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  3. Teresa H. Meng
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Beerel, P.A., Burch, J.R. & Meng, T.H. Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods in System Design 13, 37–85 (1998). https://doi.org/10.1023/A:1008666605437

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